2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)

Conference Information
Name: 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
Location: Dresden, Germany
Date: 2010-3-8 - 2010-3-12

Latest articles from this conference

Sandro Penolazzi, , Ahmed Hemani
We present a high-level method for rapidly and accurately estimating energy and performance overhead of Real-Time Operating Systems. Unlike most other approaches, which rely on Transaction-Level Modeling (TLM), we infer the information we need directly from executing the algorithmic specification, without needing to build any high-level architectural model. We distinguish two main components in our approach: first, an accurate one-time pre-characterization of the main RTOS functionalities in terms of energy and cycles; second, the development of an algorithm to rapidly predict the occurrences of such RTOS functionalities. Finally, we demonstrate the feasibility of our approach by comparing it against gate level for accuracy and against TLM for speed. We obtain a worst-case energy error of 12% against a mean speedup of 36X.
Maarten H. Wiggers, Marco J.G. Bekooij, ,
Modern embedded multimedia systems process multiple concurrent streams of data processing jobs. Streams often have throughput requirements. These jobs are implemented on a multiprocessor system as a task graph. Tasks communicate data over buffers, where tasks wait on sufficient space in output buffers before producing their data. For cost reasons, jobs share resources. Because jobs can share resources with other jobs that include tasks with date-dependent execution rates, we assume run-time scheduling on shared resources. Budget schedulers are applied, because they guarantee a minimum budget in a maximum replenishment interval. Both the buffer sizes as well as the budgets influence the temporal behaviour of a job. Interestingly, a trade-off exists: a larger buffer size can allow for a smaller budget while still meeting the throughput requirement. This work is the first to address the simultaneous computation of budget and buffer sizes.We solve this non-linear problem by formulating it as a second-order cone program. We present tight approximations to obtain a non-integral second-order cone program that has polynomial complexity. Our experiments confirm the non-linear trade-off between budget and buffer sizes.
Cristian Ferent, Varun Subramanian, Michael Gilberti, Alex Doboli
Cyber Physical Systems are distributed systems-of-systems that integrate sensing, processing, networking and actuation. Aggregating physical data over space and in time emerges as an intrinsic part of data acquisition, and is critical for dependable decision making under performance and resource constraints. This paper presents a Linear Programming-based method for optimizing the aggregation of data sampled from geographically-distributed areas while satisfy timing, precision, and resource constraints. The paper presents experimental results for data aggregation, including a case study on gas detection using a network of sensors.
Chiao-Ling Lung, Zi-Yi Zeng, Chung-Han Chou,
To conserve energy, a design which utilizes different power modes has been widely adopted. However, when a design has many different power modes, clock tree optimization (CTO) becomes very difficult. In this paper, we propose a two-level power-mode-aware CTO methodology. Among all different power modes, the chip-level CTO globally reduces clock skew among modules, whereas the module-level CTO reduces clock skew within a single module. Our experimental results show that the power-mode-aware CTO can achieve significant improvement in the worst-case condition with only a minor penalty in area.
Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.
, Eduard Stikvoort, David Tio Castro, Youri Ponomarev
The design and first measuring results of an ultra-low power 12 bit Successive-Approximation ADC for autonomous multi-sensor systems are presented. The comparator and the DAC are optimised for the lowest power consumption. The proposed design has a power consumption of 0.52 ¿W at a bitclock of 50-kHz and of 0.85 ¿W at 100-kHz with a 1.2-V supply. As far as we know, the Figure-of-Merit of 66 fJ/convertion-step is the best reported so far. The ADC was realised in the NXP CMOS 0.14 ¿m technology with an area of 0.35 mm2. Only four metal layers were used in order to allow 3D integration of the sensors.
Yu Liu, Han Liang, Kaijie Wu
This paper studies the dilemma between fault tolerance and energy efficiency in frame-based real-time systems. Given a set of K tasks to be executed on a system that supports L voltage levels, the proposed heuristic-based scheduling technique minimizes the energy consumption of tasks execution when faults are absent, and preserves feasibility under the worst case of fault occurrences. The proposed technique first finds out the optimal solution in a comparable system that supports continuous voltage scaling, then converts the solution to the original system. The runtime complexity is only (LK2). Experimental results show that the proposed approach produces near-optimal results in polynomial time.
Albert Benveniste
Cyber-Physical Systems require distributed architectures to support safety critical real-time control. Kopetz' Time-Triggered Architectures (TTA) have been proposed as both an architecture and a comprehensive paradigm for systems architecture, for such systems. To relax the strict requirements on synchronization imposed by TTA, Loosely Time-Triggered Architectures (LTTA) have been recently proposed. In LTTA, computation and communication units at all triggered by autonomous, non synchronized, clocks. Communication media act as shared memories between writers and readers and communication is non blocking. In this paper we review the different variants of LTTA and discuss their principles and usage.
Markus Damm, Javier Moreno, Jan Haase,
Wireless Sensor Networks are gaining more and more importance in various application fields. Often, energy autonomy on the node level is an essential nonfunctional constraint to be met. Therefore, when simulating such networks, the energy consumption on the node level has to be included into the simulation. To make this time consuming task feasible, an overall simulation speedup on the network level is desirable. In this paper, we propose to use techniques similar to those used in Transaction Level Models of Bus Systems.
Back to Top Top