Design and Analysis of a Modified TG Rectifier with Substrate Voltage Compensation Techniques at 45 nm Technology for High Frequency Low Power RF Energy Harvesting
Open Access
- 5 March 2020
- journal article
- Published by World Scientific and Engineering Academy and Society (WSEAS) in WSEAS TRANSACTIONS ON ELECTRONICS
- Vol. 11, 1-10
- https://doi.org/10.37394/232017.2020.11.1
Abstract
- The development of latest generation of wireless communication standards in the recent years has created enormous possibility to deploy high speed wireless network throughout the globe. There is always demand for high speed, seamless data connectivity. But it is a well-known fact that the increase in speed always makes the power consumption higher. Also while attempting to cater to the need of connectivity to a remote location, the major bottleneck is the availability of power. Hence incorporating self-sustainability to a wireless network is becoming the need of the hour. Radio frequency (RF) energy harvesting (EH) is gaining much attention in contemporary communications in this context. In the design of an EH system, the high frequency rectifier plays a significant role. Apart from several design hurdles that exist in a high frequency rectifier, to attain a high percentage conversion efficiency (PCE) at lower input power is the primary design challenge. This paper presents a design of a modified transmission gate (TG) based high frequency rectifier with two substrate voltage compensation techniques, viz. capacitor and MOS based compensation for RF EH system.The proposed capacitor and MOS based techniques enable the rectifier to achieve a PCE upto 86% and 92% at -5dBm respectively in its single stage implementation. This can be claimed to be the highest in-class efficiency as compared to recently published works. The frequency responses with both the techniques depict a wide band performance covering all popular wireless bands. The dynamic power dissipations (DPD) observed are 12nW and 16nW at -5dB, whereas the leakage power (LP) is 20x10-51W and zero respectively. Further such an performance are obtained using minimal number of transistors, viz. 4 and 5 respectively.Keywords
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