A fast-locking all-digital PLL with dynamic loop gain control and phase self-alignment mechanism for sub-GHz IoT applications

Abstract

This paper describes a fast-locking all-digital phase-locked loop (ADPLL) with dynamic loop gain control and a phase self-alignment mechanism. Compared with conventional fast-locking ADPLLs, the ADPLL proposed in this paper features the phase self-alignment mechanism to resolve overdamping caused by a large K_I. Therefore, the proposed ADPLL not only reduces locking time but also maintains jitter performance. In this paper, we used a 0.18-µm standard CMOS process with a supply voltage of 1.8 V. The experimental results indicated that the proposed ADPLL can reduce locking time by 91%. The output frequency range of the proposed ADPLL is 0.7–1 GHz, which is suitable for sub-GHz Internet of Things band applications. At 1 GHz, the power consumption was 10.93 mW, peak-to-peak jitter was 19.53 ps, locking time was 3.5 µs which is 35 T_REF, and core area was 0.291 mm².