A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures
- 10 November 2020
- journal article
- research article
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Architecture and Code Optimization
- Vol. 17 (4), 1-30
- https://doi.org/10.1145/3422667
Abstract
Vector architectures lack tools for research. Consider the gem5 simulator, which is possibly the leading platform for computer-system architecture research. Unfortunately, gem5 does not have an available distribution that includes a flexible and customizable vector architecture model. In consequence, researchers have to develop their own simulation platform to test their ideas, which consume much research time. However, once the base simulator platform is developed, another question is the following: Which applications should be tested to perform the experiments? The lack of Vectorized Benchmark Suites is another limitation. To face these problems, this work presents a set of tools for designing and evaluating vector architectures. First, the gem5 simulator was extended to support the execution of RISC-V Vector instructions by adding a parameterizable Vector Architecture model for designers to evaluate different approaches according to the target they pursue. Second, a novel Vectorized Benchmark Suite is presented: a collection composed of seven data-parallel applications from different domains that can be classified according to the modules that are stressed in the vector architecture. Finally, a study of the Vectorized Benchmark Suite executing on the gem5-based Vector Architecture model is highlighted. This suite is the first in its category that covers the different possible usage scenarios that may occur within different vector architecture designs such as embedded systems, mainly focused on short vectors, or High-Performance-Computing (HPC), usually designed for large vectors.Keywords
Funding Information
- Funding Body Award Number Consejo Nacional de Ciencia y Tecnología (Grant No. 472106)
- European Union Regional development fund (001-P-001723)
This publication has 9 references indexed in Scilit:
- Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial ProductPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2020
- Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOIIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020
- Microstructure and Crack Propagation Characteristics of SUS301L-HT Laser-MAG Hybrid-Welded JointChinese Journal of Lasers, 2020
- Paving the way for China exascale computingCCF Transactions on High Performance Computing, 2019
- Fast Adaptive Multiple Transform for Versatile Video CodingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2019
- The ARM Scalable Vector ExtensionIEEE Micro, 2017
- Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of AddersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2014
- Rodinia: A benchmark suite for heterogeneous computingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2009
- S12---The HPC Challenge (HPCC) benchmark suitePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2006