Design of an energy-efficient binarized convolutional neural network accelerator using a nonvolatile field-programmable gate array with only-once-write shifting

Abstract

This paper presents an energy-efficient hardware accelerator for binarized convolutional neural networks (BCNNs). In such BCNN accelerator, a data-shift operation becomes dominant to effectively control input/weight-data streams under limited memory bandwidth. A magnetic-tunnel-junction (MTJ)-based nonvolatile field-programmable gate array (FPGA), where the number of stored-data updating is minimized in configurable logic block, is well suited hardware platform for implementing such BCNN accelerator. Owing to the nonvolatile storage capability of the NV-FPGA, not only power consumption in data-shift operation, but also standby power consumption in idle function block is reduced without losing internal data. It is demonstrated under 45nm CMOS/MTJ process technologies that the energy consumption of the proposed BCNN accelerator is 50.7% lower than that of a BCNN accelerator using a conventional SRAM-based FPGA.