Indian Journal of Vlsi Design

Journal Information
EISSN: 25828843
Total articles ≅ 8

Articles in this journal

Published: 30 September 2022
Indian Journal of Vlsi Design, Volume 2, pp 5-10; https://doi.org/10.54105/ijvlsid.b1210.092222

Abstract:
Static Random-Access Memory (SRAM) occupies approximately 90% of total area on a chip due to high number of transistors used for a single SRAM cell. Therefore, SRAM cell becomes a power-hungry block on a chip and it becomes more prominent at lower technologies from both dynamic and static perspective. Static power consumption is due to leakage current associated with the transistors that are off and dynamic power consumption is due to charging and discharging of the circuit capacitance. As gate length or channel length decreases gate oxide thickness also scales down. Scaling down of conventional transistor results in huge tunneling of electron from gate into channel leading to higher leakage power consumption. So, transistor with metal gate, high-k dielectric and strained-Si is used which shows better result in terms of low-power consumption, better performance with acceptable delay. Among various topologies of SRAM cell 6T is considered as a suitable choice for low power applications.
Published: 30 September 2022
Indian Journal of Vlsi Design, Volume 1, pp 1-4; https://doi.org/10.54105/ijvlsid.d1209.091422

Abstract:
The evolution of portable electronic devices and their widespread application has led to an increased focus on power dissipation as one of the critical parameters. An increase in functionality requirement and design complexity on a single chip has resulted in increased power dissipation. High power dissipation has motivated study and innovation on low power circuit design techniques. Adiabatic logic has been studied as one of the design techniques to reduce power dissipation by reusing the power that was getting dissipated in conventional designs. This paper presents the application of Wave Shaping Diode Adiabatic Logic (WSDAL) to implement an ALU and analyse the improvement in power dissipation as compared to the conventional CMOS design. The WSDAL design uses a slow and time-fluctuating 2-phase sinusoidal Power Clock (PC), which supplies power as well as a clock to the designs. WSDAL uses an Ultra-Low Power Diode (ULPD) structure that operates as a wave shaping device and reduces glitches at the output. The design has been implemented in OrCAD Capture and simulated using Pspice in TSMC 180nm technology. The simulations were performed at 200MHz PC frequency and power dissipation was studied over a range of voltages from 1.4V to 2.2V. The simulations show that WSDAL ALU dissipates less power than the CMOS design. This study indicates that WSDAL-based designs have the potential to be deployed for power dissipation reduction in portable devices.
, Sarika Parihar, Vandana Niranjan
Indian Journal of Vlsi Design, Volume 1, pp 10-15; https://doi.org/10.54105/ijvlsid.c1206.031322

Abstract:
The paper presents the various trans-impedance amplifier (TIA) topologies has been studied and presented with an insight of their Gain and Bandwidth. The device parameters such as gain and bandwidth has been studied and compared for various TIA topologies. The performance of the presented topologies of TIA has been compared and summarized to get an overview. The comparison is done on the basis of its topology and device technology along with gain, bandwidth and power supply. In this paper recent advancement and future scope are also discussed.
E. N. Ganesh
Indian Journal of Vlsi Design, Volume 2, pp 16-20; https://doi.org/10.54105/ijvlsid.c1207.031322

Abstract:
The objective of the project is to design a low cost Spectral Monitor for a Space vehicle velocity measurement application, based on Doppler Shift principle by generating an radar signal source from earth station towards moving target device in space and processing received high speed analog 200MHz radar signal from target vehicle device through Antenna, analog pre-processing and FPGA based spectral analyzer. The hardware reconfigurable spectral analyzer design consist of ADC(500MSPS) Interface block, SRAM Memory(1024×16) block, Radix-2 FFT (16 bit DSP block) and LCD Display (Monitoring) driver algorithm implemented On-Chip SOC-FPGA system. The proposed algorithm can be used to meet the need of many real time application such as space exploration, wideband communication, command and control application. The desired algorithm is implemented on-chip reconfigurable hardware SOC-FPGA while keeping the cost, power and area of device low compared to general purpose processor and Embedded based microcontroller. The code architecture is described using hardware description language, VHDL and synthesized and simulated using Xilinx 12.2 ISE Design suite.
Indian Journal of Vlsi Design, Volume 1, pp 1-4; https://doi.org/10.54105/ijvlsid.c1204.031322

Abstract:
The relevance of electricity generation from renewable energy sources is growing every day in the current global energy environment. The scarcity of fossil fuels and the environmental risks connected with traditional power producing methods are the main reasons behind this. The major sources of non-conventional energy are wind and solar which can be harnessed easily. A new system design for hybrid photovoltaic and wind-power generation is introduced within this study. A Modified M.P.P.T. has been proposed to strengthen productivity of this system. The proposed approach employs the Incremental Conductance (IC) MPPT technique. Under varied climatic conditions (Solar irradiance & Temperature), IC is utilized to determine the optimum voltage output of a photo voltaic generator (P.V.G.) within the photo voltaic system (P.V.) structure. The Incremental Conductance is utilized to manage the converter’s technology having boosting function. The P.M.S.G. is used to determine the maximum voltage output for varied wind flow rates in wind turbine system. Simulations are conducted in Matlab2019b to test efficacy of the proposed MPPT. The proposed scheme’s effectiveness can be supported with simulation results.
, , , Magribatul Noora A K, Safrin Sifana T
Indian Journal of Vlsi Design, Volume 2, pp 5-9; https://doi.org/10.54105/ijvlsid.c1205.031322

Abstract:
Carry Select Adder (CSLA) is known to be the fastest adder among the conventional adder structure, which uses multiple narrow adders. CSLA has a great scope of reducing area, power consumption, speed and delay. From the structure of regular CSLA using RCA, it consumes large area and power. This proposed work uses a simple and dynamic Gate Level Implementation which reduces the area, delay, power and speed of the regular CSLA. Based on a modified CSLA using BEC the implementation of 8-b, 16-b, 32-b square root CSLA (SQRT CSLA) architecture have been developed. In order to reduce the area and power consumption in a great way we proposed a design using binary to excess 1 converter (BEC). This paper proposes an dynamic method which replaces a BEC using Common Boolean Logic.
N. Amutha Priya
Published: 10 September 2021
Indian Journal of Vlsi Design, Volume 1, pp 5-8; https://doi.org/10.54105/ijvlsid.b1202.091221

Abstract:
This Paper deals with the implementation of Harmonics distortion in distribution system by using the method of hybrid of active filter and passive filters. The active filter is used to reduce the distortion present in the output. Boost converter is used to increase the voltage level. This boost converter is connected to the inverter, which is designed by using the MOSFET as a switch. In practical application the pulses for the inverter is given by using the Arduino control. By using this hybrid method, the total harmonics distortion is reduced to below the acceptable limit. Simulation for this proposed method is done by using the MATLAB simulink. Initially, fast fourier transform may found to mitigate harmonics. But emerging technologies like Arduino control is proved to simple and economical in carrying out the same task effectively.
B.T. Krishna
Published: 10 September 2021
Indian Journal of Vlsi Design, Volume 1, pp 1-4; https://doi.org/10.54105/ijvlsid.b1201.091221

Abstract:
This paper describes implementation of CMOS based linear and non-linear analog circuitsusing operational trans conductance amplifier as the basic element. These circuits have their applications in communication and signal processing areas. In this work PSPICE is used for the simulation of various analog circuits. The corresponding results are presented.
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