III–V nanowire MOSFETs with novel self-limiting Λ-ridge spacers for RF applications

Abstract

We present a semi self-aligned processing scheme for III-V nanowire transistors with novel semiconductor spacers in the shape of Λ-ridges, utilising the effect of slow growth rate on {111}B facets. The addition of spacers relaxes the constraint on perfect alignment of gate to contact areas to enable low overlap capacitances. The spacers give a field-plate effect that also helps reducing off-state, and output conductance while increasing breakdown voltage. Microwave compatible devices with Lg = 32 nm showing fT = 75 GHz and fmax = 100 GHz are realized with the process, demonstrating matched performance to spacer-less devices but with relaxed scaling requirements.