Charge-Plasma Based Cylindrical Nanowire FET for Low-Noise and High Sensing
- 1 February 2021
- journal article
- research article
- Published by The Electrochemical Society in ECS Journal of Solid State Science and Technology
- Vol. 10 (2), 021003
- https://doi.org/10.1149/2162-8777/abe421
Abstract
A dopingless Cylindrical Nanowire Field Effect Transistor is proposed by implementing the charge plasma technique. The charge plasma technique helped in the necessary doping of the source/drain regions. The significance of using charge plasma based Nanowire FET for low-noise and higher sensing applications is investigated by analyzing the linearity parameters and compared with the Junctionless Nanowire FET. The proposed device is optimized as per the practical conditions by taking the interface trap charges into account. The interface trap charges are considered at the gate oxide-channel interface. The variation of interface trap charge (ITCs) density varies the device performance depending on the ITC polarity. The presence of ITCs can enhance device performance by tweaking the ITCs amplitude with positive polarity. The work function of the source/drain metal for the charge plasma technique is varied to get an optimized value. The higher value of source/drain metal degrades the device performance. The voltage interception point of the proposed device is greater than 5 times the actual value of the input signal. The drain current decreases drastically with the increase of source/drain work function independent of the gate bias.Keywords
This publication has 20 references indexed in Scilit:
- Doping-Less Tunnel Field Effect Transistor: Design and InvestigationIEEE Transactions on Electron Devices, 2013
- Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nmIEEE Electron Device Letters, 2012
- Theory of the Junctionless Nanowire FETIEEE Transactions on Electron Devices, 2011
- Subthreshold Regime has the Optimal Sensitivity for Nanowire FET BiosensorsNano Letters, 2009
- 5nm-gate nanowire FinFETPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- Sub 50-nm FinFET: PMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Pi-Gate SOI MOSFETIEEE Electron Device Letters, 2001
- Elementary scattering theory of the Si MOSFETIEEE Electron Device Letters, 1997
- Limitation of CMOS supply-voltage scaling by MOSFET threshold-voltage variationIEEE Journal of Solid-State Circuits, 1995
- Short-channel effects in SOI MOSFETsIEEE Transactions on Electron Devices, 1989