Design of Low Power SAR ADC Using Clock Retiming

Abstract

In digitized world power efficient Successive Approximation Register Analog-to-Digital converter(SAR-ADC) architecture are widely used in most of the electronics applications. It is very compact compared to other ADC architecture. In this proposed paper practical implementation of modified 10-bit SARADC Clock Retiming is designed. The performance of the design is analyzed by Clock Retiming with multiple input phases and multiple output phases. As a result Electrical level of glitches is also removed by Retiming without altering the functionality of the design. The transient analysis of DAC output shows gain error reduction compared to earlier design proposed, after placing the delay element to each input line of the DAC circuit. The R-2R DAC architecture of SAR-ADC is designed using Sub-micron technology. As a result ADC topology shows the low power consumption with reduction in gain error.