A Hybrid Instruction and Functional Level Energy Estimation Framework for Embedded Processors

Abstract

Energy consumption in embedded systems is becoming increasingly important especially with the increase in transistor count that needs to fit in smaller chip areas. This calls for a cross-layer effort to improve the energy consumption of an embedded design including design of energy-efficient algorithms. Consequently, we need to find ways for a programmer to quickly estimate the energy consumption of an algorithm at higher abstraction level. This work contributes towards the development of an assembly-level energy estimation framework for embedded processors. Our framework is based on a hybrid approach of instruction level power analysis (ILPA) and functional level power analysis (FLPA) techniques which results in a higher accuracy comparable to ILPA-based approaches while remaining at a higher abstraction level of FLPA for the modeling of processors. The proposed framework, therefore, provides rapid high-level energy estimation results with an accuracy consistent with the state-of-the-art approaches. As test-cases, we have used the proposed framework for two open-source IP-core processors i.e. MIPS R2000 and LEON3.