IEEE Design & Test
ISSN / EISSN: 21682356 / 21682364
Published by: Institute of Electrical and Electronics Engineers (IEEE)
Total articles ≅ 1,368
Latest articles in this journal
Published: 6 June 2023
IEEE Design & Test, pp 1-1; https://doi.org/10.1109/mdat.2023.3283351
ETHICS is evolving and becoming a conscious consideration in everyday life, while sustainability poses many long- and near-term existential questions for humanity. How do we raise the right ethical questions despite the existential choices we need to make?.
Published: 6 June 2023
IEEE Design & Test, pp 1-1; https://doi.org/10.1109/mdat.2023.3283349
Globalization of semiconductor industry has led to unprecedented challenges in design, verification, test, security and trustworthiness of contemporary electronics. With parts sourced from various suppliers across the globe, who are beyond the auspices of the original designers and system integrators, serious concerns arise regarding integrity and trustworthiness of electronic circuits, which can be compromised by malicious actors at any stage of the component manufacturing and system assembly process. Among the variety of such concerns, recycled electronics sold as new by malicious suppliers/vendors pose a key threat to mission-critical end applications such as military systems, financial institutions, transportation security, and poser distribution infrastructure. Recycled electronics may experience performance degradation due to aging and, more importantly, may have shorter-than-expected lifetime, thereby raising serious reliability and safety issues. To combat this problem, statistical methods have been proposed in the past decade as a time-efficient and cost-effective approach to identify recycled electronics sold as new. Initially demonstrating in the context of detecting recycled Integrated Circuits (ICs), such methods are based on using statistics and machine learning to outline the parametric signatures of known brand-new ICs and, thereby, weed out ICs that do not fit the expected profile. This article summarizes the current state of knowledge in recycled IC detection schemes and discusses how these methods have inspired, over time, the development of similar solutions in a plethora of domains, including identification of recycled Field Programmable Gate Arrays (FPGAs), recycled hardware components in a network, and recycled Static Random-Access Memories (SRAMs)/Flash memories .
Published: 31 May 2023
IEEE Design & Test, pp 1-1; https://doi.org/10.1109/mdat.2023.3281733
The highly tool-intensive design and validation of automated driving features brings with it significant opportunities to support ethical practices related to safety for testing and lifecycle support. This article shows how some basic principles from the IEEE 7000 standard on ethical concerns during system design can apply.
Published: 22 May 2023
IEEE Design & Test, pp 1-1; https://doi.org/10.1109/mdat.2023.3278619
Efficient design of stochastic number generators (SNGs) is critical to the area-efficiency and accuracy of stochastic computing (SC) circuits. Linear feedback shift register (LFSR)-based SNGs are commonly used in SC. To reduce the size of SNGs, we propose a new design approach that shares a combination of the permutations and negations of one LFSR’s output for several SNGs. With no hardware overhead, the approach provides SNGs with minimum average SC correlation (SCC) that result in SC circuits with higher accuracy. Compared to the prior state-of-the-art work, our approach produces stochastic bitstreams with 50% less average SCC when a 10-bit LFSR is shared between two SNGs. For an n -bit LFSR, the proposed design space consists of n ! × 2 n designs and when n > 7 it is intractable to find the design with minimum SCC by searching the whole space. To address this problem, we propose an optimized search algorithm. For m < n , the extended version of our algorithm can find a set of m different designs with minimum SCC values. We apply our approach to SC circuits for digital filters and image processing applications to demonstrate its better computational accuracy and area-efficiency compared to prior work.
Published: 18 May 2023
IEEE Design & Test, pp 1-1; https://doi.org/10.1109/mdat.2023.3277814
Deciding how best to teach ethics to computer science, data science, and engineering students remains a challenge. Broadly, two approaches are suggested: embedding ethics into courses throughout the curriculum or placing most of the ethics education into a free-standing course. Both approaches have strengths and weaknesses. In this article we describe our experience teaching a free-standing course that is placed in the university core curriculum and is a joint effort between the Philosophy and Computer Science departments. We suggest that material from Philosophy beyond moral theory has played a key role in making our course a success and that students are deeply interested in applying themes from moral theory and philosophy more generally to both life and career.
Published: 18 May 2023
IEEE Design & Test, pp 1-1; https://doi.org/10.1109/mdat.2023.3277813
Systems-on-Chip (SoCs) complexity makes security a design requirement as relevant as conventional metrics such as power, performance, and area. This work targets many-core SoCs (MCSoCs) with processing elements and hardware modules interconnected through an NoC. The main attack surface in MCSoCs is resource sharing, at the processing and communication levels. This work presents SeMAP, a method to securely execute applications in MCSoCs, using a technique for spatial isolation of applications associated with a secure communication mechanism with dedicated hardware modules. DoS and spoofing attack campaigns were ineffective in attacking applications, showing that hardware-level security mechanisms effectively add security to MCSoCs.
Published: 17 May 2023
IEEE Design & Test, pp 1-1; https://doi.org/10.1109/mdat.2023.3276936
Developing flexible, high-processing-rate, and low-power BLAKE/BLAKE2 hardware is extremely necessary for maintaining dependability, safety, and security in blockchain-based IoT systems. However, the existing hardware designs are difficult to achieve high flexibility and performance with high hardware efficiency. Therefore, this paper proposes the first flexible and scalable BLAKE/BLAKE2 coprocessor to gain high flexibility, high performance, and low power for blockchain-based IoT applications. To achieve those goals, three novel optimization techniques are proposed, including a dual-core hashing engine, a pipelined hashing engine, and a scalable four-engine coprocessor. The experimental results on FPGA and ASIC prove that our coprocessor is 3.6-65.5 times, 1.4-2.9 times, and 113-195 times better than existing works in throughput, area efficiency, and energy efficiency, respectively. Additionally, our coprocessor supports more hash functions, making it more flexible than previous architectures. Besides, the proposed coprocessor outperforms the industrial CPU/GPU by 4.7-7.1 times in the energy-delay product (EDP).
Published: 3 May 2023
IEEE Design & Test, pp 1-1; https://doi.org/10.1109/mdat.2023.3270126
Neuromorphic fabric based on emerging resistive non-volatile memories (NVMs) is a promising approach for the realization of Neural Networks (NNs) due to their low power consumption and latency based on in-memory computation. However, the non-idealities of NVMs shift activation distributions from training values, affecting post-mapping inference accuracy. Re-calibrating NNs’ batch normalization layer in a per-chip manner restores a shifted distribution close to the training distribution. However, re-calibration overhead is an issue not addressed in existing studies. Therefore, we propose approximate batch normalization and a test pattern generation method for efficient re-calibration. The proposed method requires only 0.2% of training data for re-calibration, but can regain 72.3% inference accuracy on various benchmark datasets and fault scenarios.
Published: 25 April 2023
IEEE Design & Test, pp 1-1; https://doi.org/10.1109/mdat.2023.3270234
Witnessing significant signs of a slowdown of Moore’s law and Dennard scaling has pushed leading semiconductor companies toward advanced packaging with heterogeneous integration (HI) to stay away from the challenges of monolithic IC in more shrunk technology with higher complexity. In light of the advances made in monolithic ICs, this paper explores how these promising solutions can be extended for secure HI. For this purpose, by investigating the trustworthiness of the system-in-package (SiP) supply chain, we introduce possible trust validation and attack mitigation methodologies leading to establishing the fundamentals of end-to-end secure HI.
Published: 21 April 2023
IEEE Design & Test, Volume 40, pp 5-7; https://doi.org/10.1109/mdat.2022.3221909
The current trend in energy resources shapes how computing systems will address new challenges in the following years. As a matter of fact, following the current trend, by 2040, computers will require more energy than the world’s resources can generate. In the very upcoming future, by 2025, data centers alone will consume 20% of all available electricity. A similar trend already impacts the communications side where, for example, energy consumption in mobile broadband networks and mobile terminals is comparable to data centers. These trends can only accelerate by broadening the spectrum of possible mobile applications to the Internet of Things (IoT), which will connect 50 billion devices through wireless connections to the cloud infrastructure within a few years.