We present a power-driven hierarchical framework for module/functional-unit selection, scheduling, and binding in high level synthesis. A significant aspect of algorithm design for large and complex problems is arriving at tradeoffs between quality of solution and timing complexity. Towards this end, we integrate an improved version of the very runtime-efficient list scheduling algorithm called modified list scheduling (MLS) with a power-driven simulated annealing (SA) algorithm for module selection. Our hierarchical framework efficiently explores the problem solution space by an extensive exploration of the power-driven module-selection solution space via SA, and for each module selection solution, uses MLS to obtain a scheduling and (integrated) binding (S&B) solution in which the binding is either a regular one (minimizing number of FUs and thus FU leakage power) or power-driven with mux/demux power considerations. This framework avoids the very runtime intensive exploration of both module selection and S&B within a conventional SA algorithm, but retains the basic prowess of SA by exploring only the important aspect of power-driven module-selection in a stochastic manner. The proposed hierarchical framework provides an average of 9.5% FU leakage power improvement over state of the art (approximate) algorithms that optimize only FU leakage power, and has a smaller runtime by factors of 2.5–3x. Further, compared to a sophisticated flat simulated annealing framework and an optimal 0/1-ILP formulation for total (dynamic and leakage) FU and architecture power optimization under latency constraints, PSA-MLS provides an improvement of 5.3–5.8% with a runtime advantage of 2x, and has an average optimality gap of only 4.7–4.8% with a significant runtime advantage of a factor of more than 1900, respectively.

In this paper the CMOS amplifier behaviour has been further investigated respect to the previous works in the literature. An exhaustive scenario for the EMI pollution has been considered: the injected interferences can indeed directly reach the amplifier pins or can be coupled from the PCB ground. This is a key point for evaluating also the susceptibility from the EMI coupled to the output pin, which is disclosed as a critical point. The investigated topologies are basically derived from the Miller and the Folded Cascode, which are well-known and widely used by the CMOS analog designers; all of them are re-designed in UMC 180 nm CMOS process in order to have a fair comparison.

In this paper, a new architecture of four-stage CMOS operational transconductance amplifier (OTA) based on an alternative differential AC boosting compensation called DACBC is proposed. The presented structure removes feedforward and boosts feedback paths of compensation network simultaneously. Moreover, the presented circuit uses a fairly small compensation capacitor in the order of 1 pF, which makes the circuit very compact regarding enhanced several small-signal and largesignal characteristics. The proposed circuit along with several state-of-the-art schemes from the literature have been extensively analysed and compared together. The simulation results show with the same capacitive load and power dissipation the unity-gain frequency (UGF) can be improved over 60 times than conventional nested Miller compensation. The results of the presented OTA with 15 pF capacitive load demonstrated 65° phase margin, 18.88 MHz as UGF and DC gain of 115 dB with power dissipation of 462 μW from 1.8 V.

This paper introduces a novel structure for the realization of a low voltage, low power current-mode analog to the digital converter (ADC) pipeline (12 bits). The proposed structure of the ADC is based on a novel design of a current comparator and Digital to Analog Converter (DAC) structure. This modification allows us to reach a higher speed, lower voltage, and lower power dissipation. ELDO simulators using 0.18 μm, CMOS and TSMC parameters are performed to confirm the workability of this architecture. The proposed ADC is powered with a 1 V supply voltage. It is characterized by wide conversion frequency (350 MHz) and low power consumption that is 2.76 mW.

In this work, we propose an approximate and energy-efficient CORDIC method, based on a trigonometric function spatial locality principle derived from benchmarks profiling. Successive sine/cosine computation requests cover more than 50% when the absolute phase difference is at most ten degrees. Consequently, this property suggests an optimized circuit implementation, both iterative or a succession of microrotation modules, where the last CORDIC requires fewer iterations, reducing the latency and the total energy budget at the same precision of two separate and independent instances. Thus, this simple design strategy allows significant area and energy dissipation in general-purpose VLSI architectures, but it introduces also dramatically optimizations in applicationspecific embedded systems used in the area of signal processing and radio frequency communication. In this contribution, we introduce a method, the hardware overhead and the energy budget per single cycle. Simulation results show the total energy saving in considered benchmarks is 40% in pipelined and iterative general purposes CORDIC. Furthermore, our application-specific systems (fast Fourier transform and digital oscillators for radiofrequency down conversions) show remarkable cycle savings when the successive sine/cosine computation requests are more than 70%. Finally, in this work, we extend the proposed approach to whichever phase difference less than 26.56° , as a variable for the second CORDIC number of angle rotations.

Benthic microbial fuel cells (MFCs) are promising alternatives to conventional batteries for powering underwater low-power sensors. Regarding performances (10's μW at 100's mV for cm ²-scale electrodes), an electrical interface is required to maximize the harvested energy and boost the voltage. Because the MFCs electrical behavior fluctuates, it is common to refer to maximum power point tracking (MPPT). Using a sub-mW flyback converter, this paper compares the benefit of different MPPT strategies: either by maximizing the energy at the converter input or at the converter output, or by fixing the MFC operating point at its nominal maximum power point. A practical flyback has been validated and experimentally tested for these MPPT options showing a gain in efficiency in certain configurations. The results allow determining a power budget for MPPT controllers that should not exceed this gain. Eventually, considering typical MFC fluctuations, avoiding any MPPT controller by fixing the converter operating parameters may offer better performances for sub-mW harvesters.

In this paper, an extensive review of the available publications about comparing estimations versus measurements of power consumption in FPGA technology is carried out. This study reveals that the variety of experimental setups makes it difficult to elaborate solid studies departing from the results of different researchers using meta-analysis techniques. To mitigate this problem, we propose a procedure to standardize the setup of FPGA power estimation experiments. The goal is to make as close as possible power estimations and their corresponding actual on-chip measurements. The main idea is to use a fixed arrangement composed by a parameterized pattern generator block at the input, together with a set of interchangeable IP cores utilized as reference circuits. All the blocks are mapped together inside the FPGA sample, being the clock and reset lines the sole input signals. Thus, both power estimation and actual measurements are performed to the whole system in identical conditions. In order to illustrate the method, the paper includes some examples of the proposed methodology for different cores. A set of 25 circuits have been tested in two FPGA families, obtaining relative errors in power estimation between –61.5% and 9.2%.

IoT and autonomous systems are in charge of an increasing number of sensing, processing and communications tasks. These systems may be equipped with energy harvesting devices. Nevertheless, the energy harvested is uncertain and variable, which makes it difficult to manage the energy in these systems. Reinforcement learning algorithms can handle such uncertainties, however selecting the adapted algorithm is a difficult problem. Many algorithms are available and each has its own advantages and drawbacks. In this paper, we try to provide an overview of different approaches to help designer to determine the most appropriate algorithm according to its application and system. We focus on Q-learning, a popular reinforcement learning algorithm and several of these variants. The approach of Q-learning is based on the use of look up table, however some algorithms use a neural network approach. We compare different variants of Q-learning for the energy management of a sensor node. We show that depending on the desired performance and the constraints inherent in the application of the node, the appropriate approach changes.

A low voltage supply CMOS current conveyor circuit for digital input signals from 0.25 V up to 1.2 V is presented. The circuit is optimized and pre-layout simulated in a 65 nm CMOS process technology. At the target design voltage of 1.2 V, the current conveyor has a propagation delay of 2.86 ns, an energy consumption of only 80.9 pJ, and energy-delay product (EDP) of 231 pJns for resistive load of 10 kΩ. Superior performance of this work is demonstrated through comparison with other similar published work at a frequency of 5 MHz. It is shown that the proposed circuit is suitable for digital signaling. The developed CMOS circuit perfoms correctly until 50 MHz and its EDP is 31 pJns at 10 kΩ.

CPU architecture has experienced great innovation in its architecture, from 8 bit to 64 bit, CISC to RISC, Single core to multi-core and single pipelined logic to deep multi-pipelined system. Today in an era of 64 bit architectures, 8 bits are still very relevant and has not lost its position and being used in many applications. Hence this research work deals with 8 bit CPU architecture and its features enhancement to make the 8 bit case very relevant in an era of 64 bit. The co-operative ALU, as name suggests, works in tandem with existing ALU and performs 16 bits operations. The specially designed instructions shares knowledge and efficiently handles existing ALU and Co-operative ALU to perform 8 bits and 16 bits operations. The Co-operative ALU is integrated with the 2 stage pipelined 8-bit RISC architecture ensuring that existing architecture is kept intact by way of applying new functionality in the form of an extension. The reconfigurable platform software tools are used for functionality verification and final deployment is done using reconfigurable platform hardware tools.