Journal of VLSI Design and Signal Processing

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EISSN : 2581-8449
Total articles ≅ 16
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Kamali V, S. Ewins Pon Pushpa
Journal of VLSI Design and Signal Processing, Volume 8, pp 8-16; https://doi.org/10.46610/jovdsp.2022.v08i02.002

Abstract:
The digital implementation of High-Definition Sinusoidal Pulse Width Modulation (HD-SPWM) achieves a higher accuracy and simplifies hardware design. To generate the digital PWM signal a single BRAM(Block Random Access Memory) is used. The memory allocation of the targeted FPGA device is reduced up to 43%. This reduces the number of slices (logic blocks) and LUTs, used for the implementation of HD-SPWM. The switching and sampling frequency for the generation of HD-SPWM are 20 kHz and 4 MHz respectively. The code is written in Verilog HDL and simulated in Modelsim and synthesized in Xilinx ISE. The Switching frequency achieved is 20 kHz respectively.
Bini B, Ramgopal Segu, Mahesh Kumar N.
Journal of VLSI Design and Signal Processing, Volume 8, pp 1-7; https://doi.org/10.46610/jovdsp.2022.v08i02.001

Abstract:
The increased use of wireless transmission has increased the demand for wireless radio spectrum, which can be used for a variety of social and individual benefits. As a result, radio spectrum allocation and utilization are also critical tasks. Cognitive Radio (CR) is a cutting-edge technology that claims to overcome this problem by allowing unlicensed users to access the radio spectrum without interfering with licensed users.Cognitive radio is a new technique that uses an intelligent Software Defined Radio (SDR) mechanism to assist manage the impending spectrum issue through dynamic spectrum allocation and accommodate growing data traffic. With the use of software defined protocols, SDR avoids frequent changes to the hardware structure.The key innovation of this study is the practical implementation of CR on GNU radio for real-time transmission as a primary user utilizing an energy-based spectrum sensing approach. The goal of this project is to develop a spectrum sensing approach that is best suited for detecting white spaces during SDR transmission.
B.N. Srinivasarao, K. Chandrabhushana Rao
Journal of VLSI Design and Signal Processing, Volume 8, pp 19-26; https://doi.org/10.46610/jovdsp.2022.v08i01.004

Abstract:
SRAM Memory architecture design and implementation is a challenging task for memory applications. Practical architecture was developed and used successfully using various double ended SRAM cells like 6 and 4 transistors. But for single ended SRAM cell like 5 transistors or any other number of transistors there is no specific architecture for practical applications. Conventional SRAM architecture has SRAM cell, write driver circuit along with bit inverter, Pre-charge circuit and sense amplifier which consists more, number of transistors required to handle single bit storage. In this paper SRAM architecture is implemented for single ended SRAM cell that is three transistor SRAM cell. Area is reduced by 60% with average power consumption 3.05µW and speed with 20.87GHz. Finally,28 bytes memory structure is implemented and verified its operation.
Ms. Sarika Parihar, Ms. Vineeta Singh, Vandana Niranjan
Journal of VLSI Design and Signal Processing, Volume 8, pp 1-5; https://doi.org/10.46610/jovdsp.2022.v08i01.001

Abstract:
In this paper, a similar investigation of various CMOS amplifier has been introduced. Standard gadget boundaries of transimpedance enhancer like input referred noise, power dissipation is considered and thought about. Here, the transimpedance amplifier is partitioned based on its geography and gadget innovation utilized, also execution is summed up to get the outline. The greater part of the investigation taken are performed on 0.18um technology.
Sumaiya M N, Nischitha R C, Pavithra B, Poorna M Bhat, Sindhu B K
Journal of VLSI Design and Signal Processing, Volume 7; https://doi.org/10.46610/jovdsp.2021.v07i03.003

Abstract:
Attendance management system is an important part of daily online /offline classroom evaluation. At the beginning and end of class, it is usually checked by the teacher, but it may appear that a teacher may miss someone or some students answer multiple times. Our project is based on face recognition and face recognition technologies. The concept of face recognition is to give a computer system the ability to find and recognize human faces fast and precisely in images or videos. Computers that detect and recognize faces could be applied to a wide variety of practical applications including criminal identification, security systems, identity verification etc. The entire process involved in our project can be categorized into two main processes as face detection and face recognition process. Face detection involves the detection of an input image for further processing. Face Recognition, where the detected and processed face is compared to the database of known faces to decide the correct person. The attractiveness of the proposed system is, it generates an attendance file which includes the subject name alongside other parameters which are already present. Easy accessibility of attendance using excels technology.
Jamuna S
Journal of VLSI Design and Signal Processing, Volume 7; https://doi.org/10.46610/jovdsp.2021.v07i03.002

Abstract:
RISC-V is an open, free standard architecture. As its open-source architecture, it can be used in multiple applications like embedded processors, IoT, artificial intelligence, machine learning, military and defense applications. The parameters like throughput, performance, high speed etc., become essential in designing processor architecture. Pipelining is one such unique feature supported by RISC-V ISA, which basically involves the execution of multiple instructions in single cycle. This feature helps in improving the performance of the processor architecture. RISC-V ISA supports five stages of pipelining they are instruction fetch, instruction decode, execute, memory and write-back stage. The work covered in this paper involves the design and implementation of the subsystems of the RISC-V ISA which are present in different stages of pipeline architecture. The subsystems included in this work are Floating Point Unit (FPU) of Execute stage, Branch Prediction Unit (BPU) of instruction fetch stage, Forwarding Unit of execution stage, Operand Logic of decode stage and Floating-Point register file of Write-back stage. These subsystems are designed using Verilog Hardware Description Language in Xilinx ISE. Followed by the implementation the verification of the floating-point unit and the forwarding unit is performed using System Verilog Assertions in QuestaSim. The Assertion coverage report for the same is extracted.
Gautham G, Deepika Venkatesh, A. Kalaiselvi
Journal of VLSI Design and Signal Processing, Volume 7; https://doi.org/10.46610/jovdsp.2021.v07i02.004

Abstract:
In recent years, due to the increasing density of traffic every year, it is been a hassle for drivers in metropolitan cities to maintain lane and speeds on road. The drivers usually waste time and effort in idling their cars to maintain in traffic conditions. The drivers get easily frustrated when they tried to maintain the path because of the havoc created. Transportation Institute found that the odds of a crash(or near crash) more than doubled when the driver took his or her eyes off the road formore than two seconds. This tends to cause about 23% of accidents when not following their lane paths. In worst case the fuel economy often drops and tends to cause increase in pollution about 28% to 36% per vehicle annually. This corresponds to the wastage of fuel. Owing to this problem, we proposed an ingenious method by which the lane detection can be made affordable and applicable to existing automobiles. The proposed prototype of lane detection is carried over with a temporary autonomous bot which is interfaced with Raspberry pi processor, loaded with the lane detection algorithm. This prototype bot is made to get live video which is then processed by the algorithm. Also, the preliminary setups are carried over in such a way that it is easily implemented and accessible at low cost with better efficiency, providing a better impact on future automobiles.
Midhun P Mathew, Therese Yamuna Mahesh
Journal of VLSI Design and Signal Processing, Volume 7; https://doi.org/10.46610/jovdsp.2021.v07i02.003

Abstract:
We are living in an era of wonderful events in Artificial Intelligence every day. Machine learning and computers make our work easier in several domains. Object detection is one area which greq by leaps and bounds with the advent of AI. This paper explains about a teachable machine of google which can be used by people whose have no special knowledge of AI and Machine Learning. This technology is introduced by google to help students as well as any person who has interest in studying machine learning. In this paper, we are explaining this concept with a small project to identify different classes of plant diseases using teachable machine.
Sumaiya M N, Akash U S, Aravind Sharma Kala, Sreekanth B V, Dharanendra Gowda G M
Journal of VLSI Design and Signal Processing, Volume 7, pp 42-48; https://doi.org/10.46610/jovdsp.2021.v07i01.006

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