International Journal of Reconfigurable and Embedded Systems (IJRES)

Journal Information
ISSN / EISSN : 2089-4864 / 2089-4864
Total articles ≅ 258
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Anass Deroussi, Abdessalam Ait Madi, Imam Alihamidi, Lalla Amina Charaf, Mohammed Saber, Anass Erraoui, Adnane Addaim
International Journal of Reconfigurable and Embedded Systems (IJRES), Volume 11; https://doi.org/10.11591/ijres.v11.i1.pp1-12

Abstract:
An internet of things (IoT) irrigation system is challenged by several issues, such as cost, energy consumption, and data storage. This paper proposes a novel energy-efficient, cost-effective IoT system called "NewAgriCom" to monitor agricultural field water flow. NewAgriCom works with an embedded energy harvesting system, is an autonomous remote supervisory control and data acquisition (SCADA) based on a general packet radio service (GPRS) cellular network that effectively communicates irrigation field data to the Node.js server using SIM808 EVBV3.2 modem. In javascript object notation (JSON) format, data is transmitted over the hypertext transfer protocol (HTTP) protocol to the MySQL database. Then data are transferred to the proposed IoT platform, which gives us a hand to control actuators, visualise, store and download the data. NewAgriCom can significantly reduce water consumption. It can set a schedule to control water automatically at specific times in various modes, including normal, light, and deep sleep modes. It regularly provides the location, time, signal strength, and the state of actuators with the identifier of every device remotely on the IoT Platform.
Joydeep Dey
International Journal of Reconfigurable and Embedded Systems (IJRES), Volume 11; https://doi.org/10.11591/ijres.v11.i1.pp13-24

Abstract:
In this unprecedented coronavirus crisis, telehealth had emerged as a substitute way of treatment. More specifically, paediatric children are at high risk of outside exposure now. Non critical children must be treated remotely through the tableware system. A key based secured online transmission of an intraoral image of the paediatric cavity has been proposed in this manuscript. A cavity is a dental disease occurring in children. It is mainly caused due to prolonged bacterial infections. Secured online transmission with respect to medical transactions is immensely required in telecare information systems (TIS). Data confidentiality factor is preserved with preference in this proposed technique. A parity based novel chain key (NCK) has been generated and diffused inside the intraoral paediatric cavity image. NCK generation scheme is so highly robust that it gives different combinations after each bit altering. Initial seeds are kept at the dentist and patients, to resist myriad attacks inside the wireless channel, especially during this COVID-19 period. Histogram, floating frequency, and autocorrelation were obtained with accuracy using the proposed technique. Effects were observed by flipping simultaneous bits of the initial key and results were highly acceptable. The time for the proposed key generation has been found to be 514.61 ms. The total cryptographic time has been noted as 3.5983 ms in this technique.
Hanen Abbes, Hafedh Abid, Kais Loukil, Mohamed Abid, Ahmad Toumi
International Journal of Reconfigurable and Embedded Systems (IJRES), Volume 11; https://doi.org/10.11591/ijres.v11.i1.pp49-58

Abstract:
Microprocessors and microcontrollers are mostly used to control electrical systems. These chips front into problems while monitoring systems that need heavy computing and important processing. Likewise, they fail while handling inputs and outputs speeds, especially with multi-channel photovoltaic (PV) systems. In comparison to a digital signal processor (DSP) and microcontroller implementations, field programmable gate array (FPGA) device is able to integrate a great number of PV channels and to achieve short development time, cost less and more flexible operation. As well, new control algorithms are increasingly complex; using new performing technologies is very motivating. Mainly, FPGA technology is adopted thanks to its ability to control complex applications and intelligent laws. In opposition to traditional controls, fuzzy logic based control presents more efficiency and reliability response for non-linear systems. Therefore, this paper deals with the execution of the fuzzy-based maximum power point tracking (MPPT) technique by the means of the FPGA chip for a multi-channel photovoltaic system. A multi-channel photovoltaic system is designed. Then, the FPGA circuit is investigated to get benefits from this hardware solution. Since software implementation way integrates a limited number of PV panels, hardware implementation is a promising solution that reduces execution time and therefore controls a huge number of photovoltaic channels. Finally, results of simulation of the fuzzy technique implementation on FPGA chip show that the proposed PV system controls more than 4400 channels. Therefore, the system output power is increased and the system profitability is improved.
Arif Ullah, Abdu Salam, Hanane El Raoui, Dorsaf Sebai, Mahnaz Rafie
International Journal of Reconfigurable and Embedded Systems (IJRES), Volume 11; https://doi.org/10.11591/ijres.v11.i1.pp59-70

Abstract:
Iris recognition become one of the most accurate and reliable steadfast human biometric recognition system of the decad. This paper presents an accurate framework for iris recognition system using hybrid algorithm in preprocess and feature extraction section. The proposed model for iris recognition with significant feature extraction was divided into three main levels. First level is having pre-processing steps which are necessary for the desired tasks. Our model deploys on three types of datasets such as UBIRIS, CASIA, and MMU and gets optimal results for performing activity. At last, perform matching process with decision based classifier for iris recognition with acceptance or rejection rates. Experimental based results provide for analysis according to the false receipt rate and false refusal amount. In the third level, the error rate will be checked along with some statistical measures for final optimal results. Constructed on the outcome the planned method provided the most efficient effect as compared to the rest of the approach.
Prabhakar Pujeri, Sanket S. Naik Dessai
International Journal of Reconfigurable and Embedded Systems (IJRES), Volume 11; https://doi.org/10.11591/ijres.v11.i1.pp84-92

Abstract:
To access any device, it is necessary to have an access point. A device driver is an entry point to access a device. This project is aimed to customize the Wi-Fi and general packet radio service (GPRS) device drivers in Linux OS for PXA270 (Intel Xscale ARM processor). Customizing a device driver is a special way of designing software that can be more easily ported from one architecture to another without rewriting it from scratch. The paper is discussing about the customisation of Wi-Fi and GPRS device driver in Linux OS for PXA270 (Intel Xscale ARM processor). To develop a device driver, it is necessary to understand the processor architecture and Linux kernel internals and other design constraints. Since dynamically loaded driver module is attached to the existing kernel, and any error in the driver will crash the entire system. Resource allocation and implementation for a device is one of the main concerns for device driver developers. The device resources are input/output, memory, IRQs and ports. The required toolchain to build the cross-complier for the Intel Xscale ARM processor was built on Linux platform. The customised device drivers of Wi-Fi, and GPRS was customised, and the customised images are made to port for PXA270 processor architecture on EMX-270 board. With all the supporting parameters the kernel images with drivers are build and ported efficiently. Also, a successful verification and testing had been performed for their functionalities.
Tirumale Ramesh, Khalid H Abed
International Journal of Reconfigurable and Embedded Systems (IJRES), Volume 11; https://doi.org/10.11591/ijres.v11.i1.pp93-102

Abstract:
Many-core chip multiprocessor offers high parallel processing power for big data analytics; however, they require efficient multi-level cache and interconnection to achieve high system throughput. Using on-chip first level L1 and second level L2 per core fast private caches is expensive for large number of cores. In this paper, for moderate number of cores from 16 to 64, we present a cost and performance efficient multi-level cache system with per core L1 and last level shared bus cache on each bus line of a cost-efficient geometrically bus-based interconnection. In our approach, we extracted cache hit and miss concurrencies and applied concurrent average memory access time to more accurately determine the cache system performance. We conducted least recently used cache policy-based simulation for cache system with L1, with L1/L2, and with L1/shared bus cache. Our simulation results show that an average system throughput improvement of 2.5x can be achieved by using system with L1/shared bus cache system compared to using only first level L1 or L1/L2. Further, we show that the throughput degradation for the proposed cache system is only within 5% for a single bus fault, suggesting a good bus fault tolerance.
Hameed Pasha Mohammad, H. C. Hadimani, Udara Yedukondalu, Srinivasa Rao Udara
International Journal of Reconfigurable and Embedded Systems (IJRES), Volume 11; https://doi.org/10.11591/ijres.v11.i1.pp71-83

Abstract:
Growing endless demand for digital processing technology, to perform high speed computations with low power utilization and minimum propagation delay, the metal-oxide-semiconductor (MOS) technology is implemented in the areas of very large scale integrated (VLSI) circuit technology. But MOS technology is facing the challenges in linear scaling the transistors with different channel modelling for the present day microelectronic regime. Linear scaling of MOSFET is restricted through short-channel-effects (SCEs). Use of silicon N-channel double gate MOSFETs (DG MOSFETs) in present day microelectronic regime features the short channel effect of MOSFET through a reasaonable forward transfer admittance with the characteristics of varying input capacitance values ratio. In this research paper, a distinct ρ-based model is designed to simulate SCEs through the designed silicon N-channel double gate MOSFETs with the varying front and back gate doping level and surface regions to estimate the varying junction capacitances can limit the intrusion detection systems (IDS) usage in VLSI applications. Analytical model for channel length and simulated model for total internal device capacitance through distinct ρ-based model are presented. The proposed distinct ρ-based model is suitable for silicon nanowire transistors and the effectiveness of the proposed model is validated through comparative results.
Mochammad Haldi Widianto, , Agung Trisetyarso, Edi Abdurachman
International Journal of Reconfigurable and Embedded Systems (IJRES), Volume 11; https://doi.org/10.11591/ijres.v11.i1.pp25-33

Abstract:
The development of devices connected to the internet is very significant, encouraging the creation of the internet of things (IoT). With remote systems, IoT is not enough to use in case of internet instability. By using long range (LoRa), IoT systems can now solve this problem. Millions of data make IoT-LoRa have to spend a lot of energy. This paper helps discover where recent studies offer a broad perspective on energy savings using the systematic literature review (SLR). The paper extracted 252 articles from IEEE, ACM, MDPI, Springer, Hindawi, ScienceDirect, and IAES. 44 articles passed the specified inclusion and exclusion criteria. The article focuses on knowledge about IoT-Lora, energy saving needs, energy saving factors, and the paper demographics. The author synthesizes studies for that purpose on IoT applications using LoRa.
Anil Kumar, Sanket S Naik Dessai, Shivaprasad Yadav
International Journal of Reconfigurable and Embedded Systems (IJRES), Volume 11; https://doi.org/10.11591/ijres.v11.i1.pp34-48

Abstract:
Office automation is the process using machines with the help of embedded computing perform the office activities and its tools and applications. The office automated using computer-aided processing stored, visual and audio data to simplify, improve, and automate the power saving and time management of the organization. A very important component of office automation concerns the automation of employee centred activities such as authentication, automatic alerting of appointments and automatic powering on/off personal computer. The employee image is captured using Java media framework, attendance records for all employees is gathered and processed automatically, and they can be accessed from the database on a monthly or weekly basis. The various software and hardware components of the system were developed and integrated to form the Exypnos Office System and validated on real life scenarios. Java proved to be a versatile platform for implementing a project of this nature with diverse requirements. Web camera interfacing and image capturing are implemented in the Java environment with the help of Java media framework (JMF). Java short message service (SMS) application programming interface (API) and Bluetooth technology is used for sending schedules through SMS. Radio frequency identification (RFID) systems use many different frequencies, but the most common and widely used and supported by our reader is 125 kHz. Office automation systems have more benefits to an organization. The project is implemented on MS Windows platform and in future can be implemented in Linux platform.
Matias Javier Oliva, Pablo Andrés García, Enrique Mario Spinelli, Alejandro Luis Veiga
International Journal of Reconfigurable and Embedded Systems (IJRES), Volume 10; https://doi.org/10.11591/ijres.v10.i3.pp237-248

Abstract:
Real-time acquisition and processing of electroencephalographic signals have promising applications in the implementation of brain-computer interfaces. These devices allow the user to control a device without performing motor actions, and are usually made up of a biopotential acquisition stage and a personal computer (PC). This structure is very flexible and appropriate for research, but for final users it is necessary to migrate to an embedded system, eliminating the PC from the scheme. The strict real-time processing requirements of such systems justify the choice of a system on a chip field-programmable gate arrays (SoC-FPGA) for its implementation. This article proposes a platform for the acquisition and processing of electroencephalographic signals using this type of device, which combines the parallelism and speed capabilities of an FPGA with the simplicity of a general-purpose processor on a single chip. In this scheme, the FPGA is in charge of the real-time operation, acquiring and processing the signals, while the processor solves the high-level tasks, with the interconnection between processing elements solved by buses integrated into the chip. The proposed scheme was used to implement a brain-computer interface based on steady-state visual evoked potentials, which was used to command a speller. The first tests of the system show that a selection time of 5 seconds per command can be achieved. The time delay between the user’s selection and the system response has been estimated at 343 µs.
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