2017 29th International Conference on Microelectronics (ICM)

Conference Information
Name: 2017 29th International Conference on Microelectronics (ICM)
Location: Beirut, Lebanon
Date: 2017-12-10 - 2017-12-13

Latest articles from this conference

Khaled Salah, Mohamed AbdelSalam
Abstract:
Electromagnetic (EM) simulation is currently a highly-needed planning tool in high frequency systems. The main objective of EM simulation is to find an approximate solution for Maxwell's equations that satisfies the given boundary conditions and a set of initial conditions. The most famous methods for solving EM problems are finite element method (FEM). Computations involved in FEM consume too much time. In this paper, the performance improvement from using hardware emulation (FPGAs) and GPUs to solve large numbers of linear equations is evaluated. The results show that GPUs have superior performance over FPGAs.
Ramez Hamie, Laura Ghisa, Véronique Quintard, Mikael Guegan, André Pérennou, Mouenes Fadlallah,
Abstract:
In previous papers, the authors proposed a flexible solution to extend a fixed, cabled seabed observatory with a single mode optical fiber transporting both energy and data, over several kilometers. The main topic of this paper is the optimization of the physical parameters used in our numerical model of optical propagation, in order to obtain the best fit between simulation and experimental characterization. This should facilitate the development of new network topologies.
Hussein Bazzi, Mohammad Abou Chanine, Ali Mohsen, Adnan Harb
Abstract:
This paper presents a 1V low phase noise ring based voltage-controlled-oscillator (VCO) for ultra-wide band (UWB) applications. The circuit is implemented in a 28-nm FDSOI technology. The VCO delay cell structure is characterized by a 3.75 mW power consumption and benefits from a new voltage control through the transistor body bias in order to achieve high performance with a wide tuning range. In the frequency range from 29 to 49 GHz, the lowest phase noise result is -132 dBc/Hz at 1 MHz frequency offset while operating at 49 GHz. These measurements lead to an excellent Figure of Merit (FoM) of -220 dBc/Hz.
Ghislain Takam Tchendjou, Emmanuel Simeu, Fritz Lebowsky
Abstract:
This paper presents the construction and implementation process on an FPGA platform of an objective perceived image quality, using an objective image quality assessment (IQA) method. This objective IQA uses machine learning (ML) methods to construct the models upon the features extracted from different concepts: the natural scene statistic (NSS) in spatial domain, the gradient magnitude (GM), the Laplacian of Gaussian (LoG), as well as the spectral and spatial entropies. The training phase to estimate the image quality is performed by a learning which uses two training phases to predict the objective image quality; the first to train the intermediary metrics using the classes of independent features, and the second to evaluate the image quality using the intermediary metrics. The Implementation phase on an Field Programmable Gate Array (FPGA) platform is tested on Xilinx Virtex 7 (VC707) FPGA board, and implemented using C/C++ code on Xilinx Vivado HLS.
Khaled A. Helal, Ahmed Yasser Abo Elmkarem, Al-Moataz Bellah Refaat, Taha Shawky Kamel, Kareem Ayman Mohamed, Mohamed Mahmoud Kamal, Mohamed Mostafa Abdelrahman, , Yehea Ismail
Abstract:
Neural interfaces are systems operating at the intersection of the nervous system and an internal or external device. Neuro-stimulator is one of the most important neural interfaces used to help those who experience epileptic seizures. To use this stimulator efficiently, seizure should be detected at the right time. Seizure detection is basically founded on digital signal processing by monitoring certain features of the intracranial electroencephalogram. Many of the previous researches are directed to study the detection efficacies using different systems, however, a few of them study the feasibility of implementing these systems over a computationally limited power implantable platforms. In this paper, five time-domain features and three wavelet-domain features are investigated. Following that, a high accuracy seizure detection algorithm is presented with efficient power consumption which makes it suitable for implantable neural systems. The experiment results show that the presented method achieves a sensitivity, specificity, and accuracy of 92.64%, 99.29%, and 99.16% respectively for long-term iEEG seizure detection. The area and power results are obtained from implementing the algorithms on Xilinx Spartan-6 XC6SLX45T FPGA.
Hossein Teimoori, Nassim Ravanshad, Hamidreza Rezaee-Dehsorkh
Abstract:
In this paper, an ultra-low power analog-to-digital converter (ADC) is proposed which is working based on level-crossing sampling. Level-crossing sampling is a data-compression technique utilizing specially for low-power implementation of biomedical signal acquisition systems. Despite the non-uniform nature of level-crossing sampling, the proposed ADC is implemented synchronously which leads to much lower power consumption and improved reliability. Accuracy of the ADC is improved by using a modified structure for dynamic comparators. A low-cost tuning circuit is also proposed for canceling a great portion of the background noise, which leads to a more efficient compression. The ADC is designed for ECG signal acquisition and implemented in 0.18 μm CMOS technology which consumes an ultra low power of 28 nW for 1.8 V supply voltage.
M. Younes, M. Telescu, N. Tanguy, C. Diouf, P. Morel,
Abstract:
The following topics are dealt with: field programmable gate arrays; CMOS integrated circuits; low-power electronics; medical signal processing; integrated circuit design; hardware description languages; Internet of Things; error statistics; OFDM modulation; electroencephalography.
Dina M. Ellaithy, Magdy A. El-Moursy, Ghada Hamdy, Amal Zaki,
Abstract:
Logarithmic number system (LNS) is increasingly used for low power arithmetic calculations in graphical processing unit (GPU). LNS requires less hardware. Based on uniform subdivisions and linear-Lagrange interpolation, a novel 8-subdivisions logarithmic/antilogarithmic converters are proposed. Compared with different methodologies, the proposed logarithmic/antilogarithmic converters achieve high accuracy. Also, a significant decrease in area is presented in the comparison between the proposed converters and the prior ones. Hardware implementation using shift-and-add approach is adopted to further simplify the hardware. The novel logarithmic/antilogarithmic converters are implemented and synthesized using 90 nm CMOS technology. Up to 23% and 11% decrease in relative error and area are achieved.
Hazem M. Fahmy, Gerd Baumann, ,
Abstract:
This article analyzes a typical numerical method to deal with maintaining vehicle's track for self-governed (autonomous) driving and obstacle avoidance. The new approach utilizes the established cost function definition consolidating the basic aspect of the dynamic conditions of the vehicle as position, orientation, and maximum allowed speed on road. The optimization processes minimize the cost function while determining the ideal track by fluctuating steering-angle and braking-ratio amplitudes. Vehicle-to-vehicle (V2V) communication framework is viably used through providing data on maximal road speed and road's obstacle dimensions. The parametric definition of obstacles creates an adaptable domain for low and high-speed simulations. The minimal number of influential optimization variables ensures a steady and direct generation of ideal results. By the current novel approach, we are independently able to move the vehicle on an arbitrary track approximated by low-order polynomials. Simulation tests are performed under vehicle's speeds of 10m/s, 18 m/s whilst utilizing most important features of Vehicle-to-vehicle communication systems.
Back to Top Top