2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

Conference Information
Name: 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)
Date: 2014-8-3 - 2014-8-6

Latest articles from this conference

, Zhe Xuan, Tom Baehr-Jones, Michael Hochberg
Abstract:
We present the design and characterization of a broadband, low-noise transimpedance amplifier (TIA) with adjustable gain-peaking, implemented in 65-nm CMOS. The TIA exhibits 40-GHz bandwidth, 20-dB gain and consumes 107 mW power. An additional continuously-tunable 12-dB gain-peaking near 40 GHz is available through a simple yet effective tuning mechanism, consuming only 14% more power. The adjustable gain-peaking functionality incorporated in the TIA can potentially reduce power consumption and complexity of an optical receiver and is highly desirable for adaptively-equalized receiver architectures. 50 Gb/s operation is demonstrated electrically as well as in an optical testbed. A low input-referred noise current of 2.5 uArms is achieved, suggesting an average optical power sensitivity of -14.6 dBm with a 0.5 A/W PD.
C. B. Hsu, J. B. Kuo
Abstract:
This paper presents a power consumption optimization methodology (PCOM) for low-power/ low-voltage single-cycle microprocessor circuit design via multi-threshold CMOS (MTCMOS) techniques. Based on the optimization methodology with the dual-threshold techniques, a 32-bit single-cycle MIPS microprocessor design has been optimized in terms of circuit design using dual-threshold HVT/SVT CMOS devices. According to SPICE simulation results, the power consumption of the 80,000-transistor 32-bit MIPS microprocessor, using a 90nm CMOS technology and operating at 1V with a 0.9-ns clock period, based on the optimization methodology with the dual-threshold technique, has been reduced by 27.23% during the standby period and 12.53% during the dynamic switching period as compared to the one using the conventional standard-threshold SVT CMOS devices.
Abstract:
Aggressive CMOS technology scaling trends exacerbate the aging-related degradation of propagation delay and energy efficiency in nanoscale designs. Recently, Power-gating has been utilized as an effective low-power design technique which has also been shown to alleviate some aging impacts. However, the use of MOSFETs to realize power-gated designs will also encounter aging-induced degradations in the sleep transistors themselves which necessitates the exploration of design strategies to utilize power-gating effectively to mitigate aging. In particular, Bias Temperature Instability (BTI) which occurs during activation of power-gated voltage islands is investigated with respect to the placement of the sleep transistor in the header or footer as well as the impact of ungated input transitions on interfacial trapping. Results indicate the effectiveness of power-gating on NBTI/PBTI phenomena and propose a preferred sleep transistor configuration for maximizing higher recovery.
Cecilia Garcia Martin, Erdal Oruklu
Abstract:
In this paper, multiple full adder circuits have been implemented using the FinFET device described by the BSIM-CMG model. A variety of adders have been selected to compare the impact of this technology and evaluate the performance advantages that can be achieved. Full adder designs tested in this work include 28 transistor mirror adder, 10 transistor complementary and level restoring carry logic adder and ultra-low power full adder (ULPFA) architectures which cover a broad spectrum of adder designs. Comprehensive simulation results demonstrate FinFET transistors' advantage in key design metrics, including reduced dynamic power, leakage current and delay. Overall, PDP gains of up to 83% is observed when compared to conventional CMOS circuits. However, FinFET pass-transistor circuits without level restorers are shown to be more vulnerable to voltage degradation compared to CMOS counterparts.
Payman Zarkesh-Ha
Abstract:
Over the years infrared imaging technology has enabled many critical applications such as thermal and spectral imaging, medical diagnostics, and remote sensing. The growth in infrared imaging technology has been made possible by dramatic technical advances in infrared sensor manufacturing, as well as improvements in algorithms for image processing. However, the most powerful existing infrared imaging systems are still far behind their biological counterparts in many aspects including energy efficiency, computational capabilities, and performance. Inspired by biological imaging systems, in this paper we present an intelligent readout circuit based upon spectrally tunable infrared nanostructure sensors, which can revolutionize multispectral remote sensing systems.
Praveen Gunturi,
Abstract:
Most of the literature on Ultra Wide Band (UWB) transmitters is focused on indoor communications. This paper presents the architecture of an Impulse Radio Ultra Wide Band (IR-UWB) transmitter for outdoor communications which complies with the FCC spectral limits. The transmitter consists of a pulse generator (PG) and a deriver circuit and has an operating frequency between 3.1 GHz and 6.4 GHz. The pulse output amplitude is ~ 700mV peak-to-peak into a 50Ω resistive load. The maximum data rate that can be achieved by the transmitter is 250Mbps at an overall power efficiency of 6.3%. The transmitter is compensated for voltage and temperature (VT) variations. The output pulse energy changes by less than 24% as the temperature varies from -55°C to 100°C, and by less than 5% as the supply voltage varies between 2.3 and 3.6V. The design is implemented in 180nm CMOS process and the simulation results with extracted R, L, C parasitics are presented.
Clement Jany, Alexandre Siligaris, Pierre Vincent, Philippe Ferrari
Abstract:
The operation of a periodically switched cross-coupled oscillator is considered in this work. First, it is shown that this architecture corresponds to a Van der Pol oscillator. Based on that, a novel analytical solution is proposed for the Van der Pol equation taking into account the time-dependent amplitude and frequency variation at the starting of oscillation. In addition, an original specific model for the pulsed oscillations is presented. Comparison with numerical simulations of the Van der Pol equation shows very good accuracy. Finally, it is shown that synchronization of the oscillations pulses on the input signal can be obtained under specific conditions.
Vahid Khojasteh Lazarjan, Khosrow Hajsadeghi
Abstract:
This paper presents a low power SAR ADC utilizing pipelining to increase the resolution up to 12 bits while maintaining a high speed sampling rate. Novel system level modifications and also new comparator architecture are proposed to optimize the power consumption. The ADC is designed and simulated in 0.18um CMOS technology by 1.2v supply voltage consuming 4.5mW power at 40MS/s sampling rate. The results indicates an effective number of bits (ENOB) of 11.04 bit and a challenging FOM of 54.9 fj/conversion which verifies the competence of proposed method.
Volnei A. Pedroni
Abstract:
Very few topics affect a larger audience of digital circuit designers than the subject of correctly designing and implementing finite state machines (FSMs) in hardware. For that purpose, it was shown recently that any FSM can be classified into one of just three categories, called regular, timed, and recursive FSMs. The main problem, highly subject to gross errors in practice and not properly covered by any EDA tool, is the implementation of the timed machines, because the timer must be simple and, more importantly, it is the FSM itself who must control the timer, deciding when (and how) it should run, stop, or be zeroed. This paper addresses this issue by presenting a detailed analysis of two timer-control strategies, along with corresponding circuits, design variations, pros and cons, and experimental results with hardware and power consumption measurements from implementations in three FPGA devices.
Srinivasa Reddy Kotha, Sumit Bajaj, Sahoo Subhendu Kumar
Abstract:
In this work, an efficient finite impulse response (FIR) filter using Residue Number System (RNS) is proposed. The chosen moduli set offers the advantage of shift and add approach. The proposed filter architecture is compared with an earlier proposed version of reconfigurable RNS FIR filter. The filters are synthesized using Cadence RTL compiler in UMC 90 nm technology. The performance of the filters are compared in terms of Area (A), Power (P), and Delay (T). The results show that the proposed architecture offers significant improvement in terms of area, delay and area-delay product(AT). Proposed approach is also verified functionally using Altera DSP Builder.
Back to Top Top