2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)

Conference Information
Name: 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)
Location: Gwalior, India
Date: 2016-12-19 - 2016-12-21

Articles from this conference

, Nitesh Agrawal
In this paper, we have shown frequency response analysis of common-emitter (CE) amplifier using bipolar charge plasma transistor (BCPT) with a device-circuit approach of mixed-mode simulation. Furthermore, the passive elements are adjusted to obtain the proper operating point (Q-point) of the circuit. The mixed-mode simulation results exhibits that maximum gain of the BJT, symmetric BCPT and asymmetric BCPT are 7.3 dB, 13.5 dB, and 13.7 dB, respectively and unity gain frequency are 813 GHz, 116 GHz, and 132 GHz, respectively. The mixed-mode simulation frequency response is also validated using transfer function equation containing pole and zero through MATLAB.
Naini Satheesh, Abhishek Mahapatra, Sudeendra Kumar K., , K. K. Mahapatra
Physical Unclonable Functions (PUF) are an emerging hardware security primitives proposed by various researchers in last one decade. PUFs are useful security architectures used for identification, authentication and cryptographic key generation. Many PUF topologies are proposed in the past targeting both ASIC and FPGA. It is nearly impossible to get two PUF circuits with same characteristics for the same design. PUFs make use of random process variation occurring during manufacturing of IC which is uncontrollable. The most versatile PUF is ring oscillator (RO) PUF, in which the frequencies of ring oscillators are compared to produce the PUF response. The conventional approach consumes large number of ring oscillators and requires all RO's to be mutually symmetric. In this paper, we have proposed a RO-PUF for FPGA devices, which is capable of generating multiple output bits from each ring oscillator with better security metrics in comparison with PUF designed with similar technique. The PUF is implemented on Xilinx Spartan 3E FPGA boards and the challenge-response pairs (CRP) are verified for statistical properties.
Sudeendra Kumar K., Naini Satheesh, Abhishek Mahapatra, , K. K. Mahapatra
Large number of on-chip instruments support post-silicon validation, volume test, debug, diagnosis and in-field monitoring of an integrated circuit. The IEEE 1687-2014 (Internal JTAG or IJTAG) standard is an effective method for accessing the on-chip instruments. Streamlined access to on-chip instruments through IJTAG is prone to abuse and lead to security issues. An adversary can leak confidential data or get an access to design details of IC through IJTAG network. Recently, locking and unlocking mechanism for IJTAG is proposed to secure the access to on-chip instruments. This paper presents a novel Physical Unclonable Function (PUF) based secure access method for on-chip instruments which enhances the security of IJTAG network and reduces the routing congestion in an integrated circuit.
C. Anju, Nisha Kuruvilla, T. E. Ayoob Khan, T. A. Shahul Hameed
FinFETs and Ultrathin Body FETs are promising candidates to enhance scaling trends of CMOS technology. Wavy FinFET is a hybrid device that combines these competing tech-nologies on SOI platform to provide high density and drivability without causing area penalty. The problem associated with this device is higher leakage and lower threshold voltage. Device engineering is the only solution for this problem. This work analyses the variation in performance of Wavy FinFET under various device/channel engineering methods such as substrate doping, halo doping and retrograde doping. Variation of iso-lation oxide thickness, work function engineering, and spacer engineering have also been tried out to optimize the device. The obtained results indicate that optimized Wavy FinFET can act as a solution for low power, highly reliable device topology. Leakage power is found to be reduced by 40.39%, 30.39% and 43.75% with substrate doping., halo doping and retrograde doping, respectively. Leakage power is lowered by 35.48% and 32.25% with increase in gate work function and isolation oxide thickness respectively. By using high k spacer material 54.77% reduction in leakage is further obtained without compromising drive current. By introducing structure modification such as ADSE, symmetric and asymmetric Dual k wavy FinFET leakage power is reduced by 61.35%, 44.19% and 28.25% respectively.
Saurabh B. K., Siddharth R. K., Nithin Kumar Y.B., Shivnarayan Patidar, Vasantha M. H., B. K. Saurabh, Y. B. Nithin Kumar, M. H. Vasantha
A realization of on-chip large resistance using aswitched-capacitor series to parallel topology is presented in thispaper. Using this scheme, a band-pass filter for various biomedicalapplications such as EEG, ECG, EOG at a very low cornerfrequency upto 0.01 Hz in 180 nm CMOS, N-well technology with1.8 V supply voltage and was simulated using Cadence Spectresimulator. Simulation results show that the band pass filter wasdesigned with different bandwidth ranges for various biomedicaldevice application.
The sensing ability of Ni-doped SWCNT has been evaluated in presence of isopropanol (IPA) molecule, using density functional theory. The fundamental model for this work has been built on (7, 0) zigzag CNT (Ni-doped) with adsorbed IPA molecule on sidewall of CNT. Charge transfer from nanotube surface to molecule and high adsorption energy made the sensor more conductive after adsorption. Semiconducting to metallic transfer and abrupt enhancement in current confirms the presence of isopropanol molecule near the surface.
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