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(searched for: doi:10.1145/3140659.3080256)
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Brandon Lucia, Brad Denby, Zachary Manchester, Harsh Desai, Emily Ruppel, Alexei Colin
GetMobile: Mobile Computing and Communications, Volume 25, pp 16-23; https://doi.org/10.1145/3471440.3471446

Abstract:
As rocket launch cadences increase, access to space rises dramatically - setting the stage for the next space industry surge. New, smaller, and less expensive satellites - now "nanosatellites" - can be deployed en masse to form constellations of hundreds, thousands, or even tens of thousands of devices [27, 40, 41, 16, 17, 18, 43]. A constellation of nanosatellites equipped with sensors (e.g., visual or hyperspectral cameras, particle detectors, or magnetometers) and radios provides a first-time opportunity for orbital swarm sensing to synthesize data from the unique vantage point of low-Earth orbit (LEO).
Marco Minutoli, Vito Giovanni Castellana, Cheng Tan, Joseph Manzano, Vinay Amatya, Antonino Tumeo, David Brooks, Gu-Yeon Wei
Proceedings of the 39th International Conference on Computer-Aided Design; https://doi.org/10.1145/3400302.3415781

Abstract:
Next-generation systems, such as edge devices, will have to provide efficient processing of machine learning (ML) algorithms, along with several metrics, including energy, performance, area, and latency. However, the quickly evolving field of ML makes it extremely difficult to generate accelerators able to support a wide variety of algorithms. Simultaneously, designing accelerators in hardware description languages (HDLs) by hand is laborious and time-consuming, and does not allow quick exploration of the design space. This paper discusses the SODA synthesizer, an automated open-source high-level ML framework-to-Verilog compiler targeting ML Application-Specific Integrated Circuits (ASICs) chiplets based on the LLVM infrastructure. The SODA synthesizers will allow implementing optimal designs by combining templated and fully tunable IPs and macros, and fully custom components generated through high-level synthesis. All these components will be provided through an extendable resource library, characterized by commercial and open-source logic design flows. Through a closed-loop design space exploration engine, developers will quickly explore their hardware designs along different dimensions.
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