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(searched for: Instruction Level Energy Consumption Estimation of Embedded Processor)
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Sadia Shamas, Muhammad Adeel Pasha, Shahid Masud
2020 IEEE International Symposium on Circuits and Systems (ISCAS) pp 1-5; doi:10.1109/iscas45731.2020.9180607

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Vittoriano Muttillo
2019 8th Mediterranean Conference on Embedded Computing (MECO) pp 1-5; doi:10.1109/meco.2019.8760288

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V. A. Kulkarni,
European Journal of Engineering and Technology Research, Volume 4, pp 40-44; doi:10.24018/ejers.2019.4.2.1144

Abstract:
Embedded systems are portable battery powered devices that have limited power resource. Hence, most of embedded systems need to meet energy constraint. Performance and energy consumption are the most important metrics for embedded system design. Estimation of performance, energy utilization and its validation are essential for embedded system design. Attempt has been made to precisely measure software energy consumption by three methods on ARM Cortex M4 processor. The results are validated with five benchmark programs. Tedious calculation of inter instruction cost has been minimized by taking it as certain percent of total energy. Percentage error between actual and estimated energy is found to be less than 5%.
Muhammad Irfan, Shahid Masud, Muhammad Adeel Pasha
2018 2nd IEEE Advanced Information Management,Communicates,Electronic and Automation Control Conference (IMCEC) pp 1-1770; doi:10.1109/imcec.2018.8469473

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V. A. Kulkarni, G. R. Udupi
European Journal of Engineering and Technology Research, Volume 2; doi:10.24018/ejers.2017.2.5.359

Abstract:
Embedded systems are used extensively in all spheres of life. Size, cost and power are the major issues in design and marketing of these products. In embedded system, the processor has to perform given task repeatedly. Power optimization need to be achieved not only at hardware level, but also at software level. Because software power contributes substantially in overall power consumption of embedded system. In this paper, a simplified method for instruction level energy estimation is presented for ARM Cortex M4 processor. Results obtained are compared with micro benchmark programs. The result shows less than -2% error in energy consumption estimation.
James Pallister, Steve Kerrison, Jeremy Morse, Kerstin Eder
Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems pp 51-59; doi:10.1145/3078659.3078666

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Neville Grech, Kyriakos Georgiou, James Pallister, Steve Kerrison, Jeremy Morse, Kerstin Eder
Proceedings of the 18th International Workshop on Web and Databases; doi:10.1145/2764967.2764974

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Christian Herglotz, Jürgen Seiler, , Arne Hendricks, Marc Reichenbach, Dietmar Fey
2015 IEEE International Parallel and Distributed Processing Symposium Workshop pp 190-195; doi:10.1109/ipdpsw.2015.58

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Sebastian Hesselbarth, Tim Baumgart, Holger Blume
2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) pp 1-8; doi:10.1109/patmos.2014.6951877

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Thomas Ducroux, Germain Haugou, Vincent Risson, Pascal Vivet
2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) pp 191-198; doi:10.1109/patmos.2013.6662173

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, Mohammad Salehi,
IEEE Transactions on Instrumentation and Measurement, Volume 62, pp 1927-1934; doi:10.1109/TIM.2013.2248288

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, Jose L. Ayala, Francky Catthoor
2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) pp 893-896; doi:10.1109/icecs.2012.6463518

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Journal of Low Power Electronics and Applications, Volume 2, pp 30-68; doi:10.3390/jlpea2010030

Abstract:
Despite the promising performance improvement observed in emerging many-core architectures in high performance processors, high power consumption prohibitively affects their use and marketability in the low-energy sectors, such as embedded processors, network processors and application specific instruction processors (ASIPs). While most chip architects design power-efficient processors by finding an optimal power-performance balance in their design, some use sophisticated on-chip autonomous power management units, which dynamically reduce the voltage or frequencies of idle cores and hence extend battery life and reduce operating costs. For large scale designs of many-core processors, a holistic approach integrating both these techniques at different levels of abstraction can potentially achieve maximal power savings. In this paper we present CASPER, a robust instruction trace driven cycle-accurate many-core multi-threading micro-architecture simulation platform where we have incorporated power estimation models of a wide variety of tunable many-core micro-architectural design parameters, thus enabling processor architects to explore a sufficiently large design space and achieve power-efficient designs. Additionally CASPER is designed to accommodate cycle-accurate models of hardware controlled power management units, enabling architects to experiment with and evaluate different autonomous power-saving mechanisms to study the run-time power-performance trade-offs in embedded many-core processors. We have implemented two such techniques in CASPER–Chipwide Dynamic Voltage and Frequency Scaling, and Performance Aware Core-Specific Frequency Scaling, which show average power savings of 35.9% and 26.2% on a baseline 4-core SPARC based architecture respectively. This power saving data accounts for the power consumption of the power management units themselves. The CASPER simulation platform also provides users with complete support of SPARCV9 instruction set enabling them to run a full operating system software stack, and hence a wide variety of benchmarking applications.
David Szczesny, Shadi Traboulsi, Felix Bruns, Sebastian Hessel, Attila Bilgic
2011 6th IEEE International Symposium on Industrial and Embedded Systems pp 232-237; doi:10.1109/sies.2011.5953666

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Roman Bourgade, Christine Rochange, Marianne De Michiel, Pascal Sainrat
2010 5th International Conference on Embedded and Multimedia Computing pp 1-7; doi:10.1109/emc.2010.5575754

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, Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Angeliki Kritikakou, Javed Absar
Ultra-Low Energy Domain-Specific Instruction-Set Processors pp 33-81; doi:10.1007/978-90-481-9528-2_3

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Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) pp 496-501; doi:10.1109/date.2010.5457153

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Tohru Ishihara
Published: 19 January 2008
High-Performance Computing pp 452-465; doi:10.1007/978-3-540-77704-5_43

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José A. De Holanda, Jecel Assumpção, Denis F. Wolf, ,
2007 International Symposium on Industrial Embedded Systems pp 345-348; doi:10.1109/sies.2007.4297358

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Jaebok Park, Hyunwoo Joe, Hyungshin Kim
Computer Vision pp 453-463; doi:10.1007/978-3-540-72685-2_43

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Donghoon Lee, , Masanori Muroyama, Hiroto Yasuura, Farzan Fallah
2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia pp 59-64; doi:10.1109/estmed.2006.321275

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S. Nikolaidis, A. Chatzigeorgiou,
Published: 1 December 2005
Computer Standards & Interfaces, Volume 28, pp 150-158; doi:10.1016/j.csi.2005.01.016

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Radu Muresan, Catherine Gebotys
ACM Transactions on Embedded Computing Systems, Volume 4, pp 415-451; doi:10.1145/1067915.1067923

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, Sheng-Yuan Wang, Yuan Dong, Gui-Lan Dai, Yang Yang
Computer Vision, Volume 3605, pp 443-448; doi:10.1007/11535409_64

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G. Ascia, V. Catania, M. Palesi,
Proceedings. 2004 NASA/DoD Conference on Evolvable Hardware, 2004.; doi:10.1109/eh.2004.1310830

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Sridhar Rajagopal, Joseph R. Cavallaro, Scott Rixner
Published: 3 September 2004
by IEEE
IEEE Micro, Volume 24, pp 54-66; doi:10.1109/mm.2004.25

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N. Kavvadias, P. Neofotistos, S. Nikolaidis, K. Kosmatopoulos, Th. Laopoulos
Proceedings of the 20th IEEE Instrumentation Technology Conference (Cat. No.03CH37412), Volume 2, pp 981-986 vol.2; doi:10.1109/imtc.2003.1207899

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Keith D. Cooper, Li Xu
Computer Vision pp 288-305; doi:10.1007/978-3-540-24644-2_19

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T.K. Tan, A. Raghunathan, N.K. Jha
2003 Design, Automation and Test in Europe Conference and Exhibition; doi:10.1109/date.2003.1253742

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A. Bona, M. Sami, , , V. Zaccaria, R. Zafalon
Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition; doi:10.1109/date.2002.998484

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Hztzefa Mehta, Robert Michael Owens, Mary Jane Irwin
1996 IEEE International Conference on Acoustics, Speech, and Signal Processing Conference Proceedings; doi:10.1109/icassp.1996.550589

N. Kroupis, M. Dasigenis, A. Argyriou, K. Tatas, D. Soudris, A. Thanailakis, N. Zervas, C.E. Goutis
Proceedings 2001 International Conference on Image Processing (Cat. No.01CH37205), Volume 3, pp 728-731 vol.3; doi:10.1109/icip.2001.958222

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J.-G. Cousin, O. Sentieys, D. Chillet
2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), Volume 2, pp 621-624 vol.2; doi:10.1109/iscas.2000.856405

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Tat Kee Tan, A. Raghunathan, , N. K. Jha
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 21, pp 1037-1050; doi:10.1109/tcad.2002.801094

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S. Nikolaidis, N. Kavvadias, P. Neofotistos, K. Kosmatopoulos, T. Laopoulos, L. Bisdounis
Transactions on Petri Nets and Other Models of Concurrency XV pp 71-80; doi:10.1007/3-540-45716-x_8

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S. Nikolaidis, Th. Laopoulos
Computer Standards & Interfaces, Volume 24, pp 133-137; doi:10.1016/s0920-5489(02)00008-9

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A. Bona, M. Sami, , , V. Zaccaria, R. Zafalon, Bona A., Sami M., Sciuto D., Silvano C., et al.
2006 43rd ACM/IEEE Design Automation Conference pp 886-891; doi:10.1109/dac.2002.1012747

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Sheayun Lee, Andreas Ermedahl, Sang Lyul Min, Naehyuck Chang
ACM SIGPLAN Notices, Volume 36, pp 1-10; doi:10.1145/384196.384201

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A. Sama, M. Balakrishnan, J.F.M. Theeuwen, Sama A.
Proceedings of the 2000 international symposium on Symbolic and algebraic computation symbolic and algebraic computation - ISSAC '00 pp 191-196; doi:10.1109/lpe.2000.155276

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D. Sarta, D. Trifone, G. Ascia
Proceedings IEEE Alessandro Volta Memorial Workshop on Low-Power Design; doi:10.1109/lpd.1999.750419

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