Development of a High Level Power Estimation Framework for Multicore Processors

Abstract

This paper presents a tool to estimate power consumption of multicore processors from the instruction level as well as the architectural level, specifically the dynamic power. In embedded systems, power optimization/estimation is a must because most of them are battery operated having limited life. For different application, a system or a processor consumes different amount of power. Knowing the statistics of power at the earlier stage can make the development process more efficient. For this purpose, we have used the Instruction Accurate Simulator Imperas, which gives an interface to define virtual platforms, also known as Open Virtual Platforms to run applications on it. Instruction tracing or profiling is done to get all the instructions that are run by each processor at the architectural level and then power of each instruction is inserted to result the total power consumed by the core. Models of the OR1K and MIPS32 are used for simulating the virtual platforms which are available in the form of dynamic libraries. The instruction profiling is done at the assembly level, while the platform and applications are in the form of C language. Energy consumed by each core is also calculated by assuming the CPI (Cycles per instruction) equal to 1.