Design of Diversified Low Power and High-Speed Comparators using 45nm Cmos Technology

Abstract

At Present, portable battery-operated devices are enhancing due to low power consumption and high-speed applications, The designed circuit with feedback are used to design novel circuits. If the comparator having feedback are without clock signal. The comparators are mainly designed to minimize the power consumption and with good accuracy because of clock signal, if the clock signal is there, it is used to drive the circuit with low current. But in the existed design the circuit is with high power and current. These drawbacks are overcome by using the projected designed comparator. The Projected comparator design is with reduced power consumption, propagation delay, currents and with a smaller number of transistors. The comparators are useful in analog to digital converters. And this is simulated by using 45 nm CMOS technology Cadence Virtuoso tool.