An improved instruction-level energy model for RISC microprocessors

Abstract

The power and energy consumed by a chip have become primary design constraints for embedded systems and are largely affected by software. However, there is a gap between software and hardware that makes it hard to predict which code consumes the least power before running it. Therefore, it is vital to discover which factors affect a program's energy consumption. In this paper we present an instruction-level power model for a single core, in-order RISC processor architecture. We do not analyze each instruction individually, but we study the average power and running time instead. We find the power in a processor is nearly constant, no matter what instructions are run, but the IO port power is related to the behavior of the program. Furthermore, we provide a model that takes the cache miss rate into consideration.