Performance Analysis of CMOS Circuits using Shielded Channel Dual Gate Stack Silicon on Nothing Junctionless Transistor
- 30 August 2021
- journal article
- Published by Blue Eyes Intelligence Engineering and Sciences Engineering and Sciences Publication - BEIESP in International Journal of Engineering and Advanced Technology
- Vol. 10 (6), 1-10
- https://doi.org/10.35940/ijeat.e2576.0810621
Abstract
In this paper it has been demonstrated that a shielded channel made by varying the side gate length in silicon-on-nothing junctionless transistor not only improves the short channel effect but also improve the performance of CMOS circuits of this device. The proposed device shielded channel dual gate stack silicon on nothing junctionless transistor (SCDGSSONJLT) drain induced barrier lowering (DIBL), cut-off frequency and subthreshold slope are improved by 20%, 39% and 20% respectively over the single material gate silicon on insulator junctionless transistor (SMG SOI JLT). The proposed device CMOS inverter fall time Tf (pS) and noise margin improves by 50% and 10% compare to shielded channel silicon on insulator junctionless transistor (SCSOIJLT). It has been observed that circuit simulation of CMOS inverter, NAND and NOR of proposed device. The static power dissipation in the case of proposed SCDGSSONJLT device are reduced by 45%, 81% and 83% respectively over the SMGSOIJLT. Thus, significant improvement in DIBL, cut-off frequency, propagation delay and static power dissipation at low power supply voltage shows that the proposed device is more suitable for low power CMOS circuits.Keywords
This publication has 28 references indexed in Scilit:
- A Dual-Material Gate Junctionless Transistor With High-$k$ Spacer for Enhanced Analog PerformanceIEEE Transactions on Electron Devices, 2013
- Threshold voltage, and 2D potential modeling within short-channel junctionless DG MOSFETs in subthreshold regionSolid-State Electronics, 2013
- Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuitsMicroelectronics Journal, 2012
- Junctionless Nanowire Transistor (JNT): Properties and design guidelinesSolid-State Electronics, 2011
- High-$k$ Gate Stack Properties in SON Transistor Given by Voltage and Temperature Dependence of Random Telegraph SignalIEEE Transactions on Electron Devices, 2011
- Nanowire transistors without junctionsNature Nanotechnology, 2010
- Reduced electric field in junctionless transistorsApplied Physics Letters, 2010
- Silicon-on-Nothing MOSFETs: Performance, Short-Channel Effects, and Backgate CouplingIEEE Transactions on Electron Devices, 2004
- Modeling the tunnelling current in reverse-biased p/n junctionsSolid-State Electronics, 1990
- Zener tunneling in semiconductorsJournal of Physics and Chemistry of Solids, 1960