Hardware-assisted power estimation for design-stage processors using FPGA emulation
- 1 September 2014
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
Abstract
This paper presents the application of an accurate power estimation model for design-stage processors that can be mapped onto an FPGA together with the functional emulation. Based on a hybrid functional level power analysis (FLPA) and instruction level power analysis (ILPA) approach, the model enables the estimation of application-specific power consumption and energy per task at very early design stages of programmable embedded processors. The extremely short execution time of the emulated power model compared to gate-transfer level (GTL) power simulation allows both hardware and software designers to constantly optimize their implementations for low-power iteratively in different design stages. The power consumption modeling methodology used for this work and necessary considerations for FPGA implementation are described. The presented model is validated against GTL power simulation with respect to execution time and precision by benchmarking for an exemplary embedded RISC processor core, the LEON2. Benchmarking results yield a percentage mean absolute error (%MAE) of less than 9% and normalized root mean square error (NRMSE) of less than 6% while reducing power estimation time from several hours down to a few milliseconds. Finally, a case-study with varying real-world input data sizes has been performed on different software implementations of JPEG encoder and decoder applications and optimized processor core. With software and hardware optimizations applied, required energy per task has been reduced by up to 46% for the JPEG encoder and 39% for the JPEG decoder, demonstrating the advantage of the presented approach.Keywords
This publication has 13 references indexed in Scilit:
- Hardware-accelerated design space exploration framework for communication systemsAnalog Integrated Circuits and Signal Processing, 2013
- Accelerating early design phase differential power analysis using power emulation techniquesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2011
- A Multi-Granularity Power Modeling Methodology for Embedded ProcessorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010
- Full-system chip multiprocessor power evaluations using FPGA-based emulationPublished by Association for Computing Machinery (ACM) ,2008
- Power emulationPublished by Association for Computing Machinery (ACM) ,2005
- The impact of technology scaling on lifetime reliabilityPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2004
- From ASIC to ASIP: the next design discontinuityPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A portable and fault-tolerant microprocessor based on the SPARC v8 architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Function-level power estimation methodology for microprocessorsPublished by Association for Computing Machinery (ACM) ,2000
- Power analysis and minimization techniques for embedded DSP softwareIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1997