On Predictable Reconfigurable System Design
Open Access
- 9 February 2021
- journal article
- research article
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Architecture and Code Optimization
- Vol. 18 (2), 1-28
- https://doi.org/10.1145/3436995
Abstract
We propose a design methodology to facilitate rigorous development of complex applications targeting reconfigurable hardware. Our methodology relies on analytical estimation of system performance and area utilisation for a given specific application and a particular system instance consisting of a controlflow machine working in conjunction with one or more reconfigurable dataflow accelerators. The targeted application is carefully analyzed, and the parts identified for hardware acceleration are reimplemented as a set of representative software models. Next, with the results of the application analysis, a suitable system architecture is devised and its performance is evaluated to determine bottlenecks, allowing predictable design. The architecture is iteratively refined, until the final version satisfying the specification requirements in terms of performance and required hardware area is obtained. We validate the presented methodology using a widely accepted convolutional neural network (VGG-16) and an important HPC application (BQCD). In both cases, our methodology relieved and alleviated all system bottlenecks before the hardware implementation was started. As a result the architectures were implemented first time right, achieving state-of-the-art performance within 15% of our modelling estimations.Keywords
Funding Information
- Maxeler, Intel, and Xilinx is gratefully acknowledged
- United Kingdom EPSRC (EP/L016796/1, EP/N031768/1, EP/P010040/1, EP/S030069/1, and EP/L00058X/1)
This publication has 45 references indexed in Scilit:
- Hardware Development: Agile and Co-DesignPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2015
- A million spiking-neuron integrated circuit with a scalable communication network and interfaceScience, 2014
- Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis ToolsInternational Journal of Reconfigurable Computing, 2013
- Hardware Acceleration of Genetic Sequence AlignmentLecture Notes in Computer Science, 2013
- Rapid computation of value and risk for derivatives portfoliosConcurrency and Computation: Practice and Experience, 2011
- RooflineCommunications of the ACM, 2009
- Reconfigurable computing: architectures and design methodsIEE Proceedings - Computers and Digital Techniques, 2005
- Design methodologies based on hardware description languagesIEEE Transactions on Industrial Electronics, 1999
- Fixed-point optimization utility for C and C++ based digital signal processing programsIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1998
- Confinement of quarksPhysical Review D, 1974