Using reconfigurable multi-core architectures for safety-critical embedded systems
- 12 December 2016
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE) in 2016 IEEE/AIAA 35th Digital Avionics Systems Conference (DASC)
Abstract
With the onset of multi- and many-core chips, the single-core market is closing down. Those chips constitute a new challenge for aerospace and safety-critical industries in general. Little is known about the certification of software running on these systems. There is therefore a strong need for developing software architectures based on multi-core architectures, yet compliant with safety-criticality constraints. This paper presents a reconfigurable multi-core architecture and the safety-criticality constraints for airborne systems. The last section uses the current certification guidance to explain how the architecture can satisfy these constraints even with dynamic features activated.Keywords
This publication has 3 references indexed in Scilit:
- REDEFINEACM Transactions on Embedded Computing Systems, 2009
- Use of multicore processors in avionics systems and its potential impact on implementation and certificationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2009
- DAG-consistent distributed shared memoryPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002