Write-awareness prefetching for non-volatile cache in energy-constrained IoT device

Abstract

Large-sized cache is beneficial to improve CPU performance especially for IoT applications with huge amount of data. However, large-sized SRAM cache also increases chip area and energy which is not friendly to resources limited IoT terminals. The STT-RAM with high storage density and near zero leakage is regarded as an ideal technology to replace SRAM. Prefetching is a vital method to hide the access latency of off-chip memory. Nevertheless, traditional prefetchers for SRAM is inadequate for MRAM cache with read-write asymmetry. Aggressive prefetching for STT-RAM cache would cause cache congestion and dynamic energy rise because of STT-RAM long write latency and high write energy. In response to the above problems, this paper novelty proposes WANCP (Write-awareness Adaptive Non-volatile Cache Prefetch), which adaptively adjusts the prefetch aggressiveness according to the saturation of MSHR (Miss-status Handling Registers) in the L2 cache. Experiments show that, for applications that are sensitive to L2 cache capacity, the CPU performance with STT-RAM L2 cache can be improved by up to 33.2% and 10.9 % on average compared to the same sized SRAM L2 cache. The proposed WANCP can further improve the CPU performance 0.4 % on average, and reduce the prefetch energy by 9.4% on average.