Gate‐all‐around nanowire vertical tunneling FETs by ferroelectric internal voltage amplification

Abstract

This work illustrates the most effective way of utilizing the ferroelectricity for tunnel field-effect transistors (TFETs). The ferroelectric (Hf_0.5Zr_0.5O₂) in shunt with gate-dielectric is utilized as an optimized metal-ferroelectric-semiconductor (OMFS) option to improve the internal voltage (V_int) for ample utilization of polarization and electric fields of Hf_0.5Zr_0.5O₂ across the tunneling region. The modeling of V_int signifies 15-20% and 5% reduction in tunneling length (λ) and energy barrier width (Δφ) than the nominal metal-ferroelectric-insulator-semiconductor (MFIS) options. Furthermore, the TFET geometry with the scaled-epitaxy region as vertical TFET (VTFET), strained Si_0.6Ge_0.4 as source, and gate-all-around nanowire options are used as an added advantage for further enhancement of TFET's performance. As a result, the proposed design (OMFS-VTFET) achieves superior DC and RF performances than the MFIS option of ferroelectric. The figure of merits in terms of DC characteristics in the proposed and optimized structure are of improved on-current (= 0.23 mA/μm), high on-to-off current ratio (= 10¹¹), steep subthreshold swing (= 33.36 mV/dec), and superior unity gain cut-off frequency (≥ 300 GHz). The design is revealed as energy efficient with 2-to-3 order reduction of energy-efficiency in both logic and memory applications.