Minimizing Temperature Nonuniformity by Optimal Arrangement of Hotspots in Vertically Stacked Three-Dimensional Integrated Circuits
- 29 June 2020
- journal article
- research article
- Published by ASME International in Journal of Electronic Packaging
- Vol. 142 (4)
- https://doi.org/10.1115/1.4047471
Abstract
The semiconductor packaging technologies have seen its growth from multichip module (MCM), system in package (SiP), system on chip (SoC) to the heterogeneous integration of the MCM. Thermal management of multichip vertically integrated systems poses additional constraints and limitations beyond those for single chip modules. Three-dimensional-integrated circuits (3D ICs) technology is a potential approach for next-generation semiconductor packaging technologies. A 3D IC is formed by vertical interconnection of multiple substrates containing active devices which offer reduced die footprint and interconnect length. This paper discusses the optimal arrangement of two hotspots on each layer of a two-die stacked 3D IC. An analytical heat transfer model for prediction of three-dimensional temperature field of a 3D IC based on the solution of governing energy equations has been developed and used for this study. The model is subject to adiabatic boundary conditions at the walls except for the bottom wall which is subject to convective boundary condition. A feed-forward back propagation artificial neural network (ANN) is employed for obtaining the functional relationship between the location of the hotspots and the objectives. Genetic algorithm is employed for solving two nonconflicting objective functions subject to set of constraints. The first objective aims to minimize the maximum temperature on both layers, and the second objective aims to achieve temperature uniformity in the layers. The results of the optimization study are expected to provide recommendations on the design guidelines for arranging hotspots on vertically stacked substrates.Keywords
This publication has 16 references indexed in Scilit:
- Experimental and Numerical Investigation of Interdie Thermal Resistance in Three-Dimensional Integrated CircuitsJournal of Electronic Packaging, 2017
- Experimental investigation on the heat transfer performance of a PCM based pin fin heat sink with discrete heatingInternational Journal of Thermal Sciences, 2017
- Multi-objective geometric optimization of a PCM based matrix type composite heat sinkApplied Energy, 2015
- An explicit analytical model for rapid computation of temperature field in a three-dimensional integrated circuit (3D IC)International Journal of Thermal Sciences, 2015
- Optimal Distribution of Discrete Heat Sources Under Mixed Convection—A Heuristic ApproachJournal of Heat Transfer, 2014
- Thermal–electrical co-optimisation of floorplanning of three-dimensional integrated circuits under manufacturing and physical design constraintsIET Computers & Digital Techniques, 2011
- Review of utilization of genetic algorithms in heat transfer problemsInternational Journal of Heat and Mass Transfer, 2009
- Optimization of the location of multiple discrete heat sources in a ventilated cavity using artificial neural networks and micro genetic algorithmInternational Journal of Heat and Mass Transfer, 2008
- Heat Conduction in Multilayered Rectangular DomainsJournal of Electronic Packaging, 2007
- Training feedforward networks with the Marquardt algorithmIEEE Transactions on Neural Networks, 1994