Dataflow-Architecture Co-Design for 2.5D DNN Accelerators using Wireless Network-on-Package
- 18 January 2021
- conference paper
- conference paper
- Published by Association for Computing Machinery (ACM) in Proceedings of the 26th Asia and South Pacific Design Automation Conference
Abstract
Deep neural network (DNN) models continue to grow in size and complexity, demanding higher computational power to enable real-time inference. To efficiently deliver such computational demands, hardware accelerators are being developed and deployed across scales. This naturally requires an efficient scale-out mechanism for increasing compute density as required by the application. 2.5D integration over interposer has emerged as a promising solution, but as we show in this work, the limited interposer bandwidth and multiple hops in the Network-on-Package (NoP) can diminish the benefits of the approach. To cope with this challenge, we propose WIENNA, a wireless NoP-based 2.5D DNN accelerator. In WIENNA, the wireless NoP connects an array of DNN accelerator chiplets to the global buffer chiplet, providing high-bandwidth multicasting capabilities. Here, we also identify the dataflow style that most efficienty exploits the wireless NoP's high-bandwidth multicasting capability on each layer. With modest area and power overheads, WIENNA achieves 2.2X-5.1X higher throughput and 38.2% lower energy than an interposer-based NoP design.Keywords
This publication has 24 references indexed in Scilit:
- Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters CompressionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2020
- Understanding the Impact of On-chip Communication on DNN Accelerator PerformancePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2019
- Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile DevicesIEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2019
- ReplicaPublished by Association for Computing Machinery (ACM) ,2019
- An Asymmetric, Energy Efficient One-to-Many Traffic-Aware Wireless Network-in-Package Interconnection Architecture for Multichip SystemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2018
- On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore SystemsInternational Conference on Acoustics, Speech, and Signal Processing (ICASSP), 2017
- TETRISPublished by Association for Computing Machinery (ACM) ,2017
- ShiDianNaoPublished by Association for Computing Machinery (ACM) ,2015
- The last barrier: on-chip antennasIEEE Microwave Magazine, 2013
- An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier InterconnectsIEEE Journal of Solid-State Circuits, 2012