A Transistor-Level DFF Based on FinFET Technology for Low Power Integrated Circuits

Abstract

With the downscaling of semiconductor devices and increased fabrication complexity, the feature size and threshold voltage (Vth) of transistors are also decreased significantly. This further makes the static power of standard cell library a crucial design challenge. In this paper, transistor-level gate length biasing (TLLB) method is utilized to optimize the static power consumption of a Scan D Flip-Flop (DFF) based on the Semiconductor Manufacturing International Corporation (SMIC) 14 nm FinFET standard cell library. An improvement in both static power consumption and speed have been achieved by utilizing the TLLB optimization which can be further implemented in a variety of complex circuit designs. Furthermore, we have synthesized ARM A72 design using the standard cell library including TLLB DFF which can save 26% static power consumption compared to that with short channel DFF. The frequency is faster with shorter delay than the one using long channel DFF.