An instruction-level methodology for power estimation and optimization of embedded VLIW cores
- 25 June 2003
Abstract
Summary form only given. The overall goal of this work is to define an instruction-level power macro-modeling and characterization methodology for VLIW embedded processor cores. The approach presented in this paper is a major extension of the work previously proposed, targeting an instruction-level energy model to evaluate the energy consumption associated with a program execution on a pipelined VLIW core. Our ongoing work aims at defining a power optimization technique based on the proposed model. The technique consists of a spatial rescheduling of the operations within the same long instruction to reduce their instruction power overhead.Keywords
This publication has 2 references indexed in Scilit:
- Instruction-level power estimation for embedded VLIW coresPublished by Association for Computing Machinery (ACM) ,2000
- Power exploration for embedded VLIW architecturesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2000