Vector Runahead for Indirect Memory Accesses
Published: 29 March 2022
in IEEE Micro
Abstract: Vector Runahead delivers extremely high memory-level parallelism even for chains of dependent memory accesses with complex intermediate address computation, which conventional runahead techniques fundamentally cannot handle and therefore have ignored. It does this by rearchitecting runahead to use speculative data-level parallelism, rather than work-skipping, as its primary form of extracting more memory-level parallelism in runahead mode than a true execution can, which we hope will bring about an entirely new dimension for high-performance processors.
Keywords: Registers / Prefetching / Program processors / Pipeline processing / Codes / Out of order
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