LOW POWER CIRCUIT FOR BRENT-KUNG ADDER BASED ON ADIABATIC LOGIC

Abstract

Adiabatic logic circuit designs are used to reduce power dissipation in any circuits. For low power and low noise emission applications, adder plays a vital role. The Complementary Metal Oxide Semiconductor (CMOS) design of 16-bit Brent-kung adder provides less number of gates but it generates high power due to switching activities of the design. To overcome this problem, 16-bit Brent-kung adder is designed using complementary Pass Transistor Energy Recovery adiabatic Logic (CPERL) with less number of gates. Also, low power dissipation is achieved which can be used for long life battery operations. The CPERL based system offers 59.97% reduction in power when compared to the conventional design. Experimental results are obtained using TANNER EDA tool 13.1.