A phase synchronization and magnitude processor VLSI architecture for adaptive neural stimulation

Abstract

A low-power VLSI processor architecture that computes in real time the magnitude, phase and phase synchronization of two input signals is presented. The processor is part of an envisioned closed-loop implantable or wearable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized in a standard 1.2 V 0.13 μm CMOS technology utilizes 41,000 logic gates. For 64 input channels, it dissipates 1.1 μ W per input, and provides 1 kS/s per-channel throughput when clocked at 1.41 MHz. The power scales linearly with the number of input channels or the sampling rate.