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Low-Power CMOS 1-Bit Full Adder using FPGA KIT & DSM Technology

A.S Keerthi Nayani Et. Al.
Turkish Journal of Computer and Mathematics Education (TURCOMAT) , Volume 12, pp 5720-5725; doi:10.17762/turcomat.v12i3.2247

Abstract: The aspire of the manuscript be near apply a 14T Full adder unit, so as to make use of little power by means of XOR and XNOR gate . The 4-bit binary adder is constructed in ripple carry adder arrangement. It has been urbanized for little power utilization in falling the no. of transistor. The power utilization be able to abridged by 49% with planned FA difference ate through regular FA. Every one replication outcome contain be approved elsewhere by with 32 nm CMOS technology. The replication outcome of 1-bit adder planned FA shows so as to the planned FA have little power utilization. The hardware accomplishment of 14T FA be agreed with Deep Sub micron Technology
Keywords: CMOS / adder / bit / 14T / little power / planned FA / power utilization

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