High-Level Synthesis of Transactional Memory
- 18 January 2021
- conference paper
- conference paper
- Published by Association for Computing Machinery (ACM) in Proceedings of the 26th Asia and South Pacific Design Automation Conference
Abstract
The rising popularity of high-level synthesis (HLS) is due to the complexity and amount of background knowledge required to design hardware circuits. Despite significant recent advances in HLS research, HLS-generated circuits may be of lower quality than human-expert-designed circuits, from the performance, power, or area perspectives. In this work, we aim to raise circuit performance by introducing a transactional memory (TM) synchronization model to the open-source LegUp HLS tool [1]. LegUp HLS supports the synthesis of multi-threaded software into parallel hardware [4], including support for mutual-exclusion lock-based synchronization. With the introduction of transactional memory-based synchronization, location-specific (i.e. finer grained) memory locks are made possible, where instead of placing an access lock around an entire array, one can place a lock around individual array elements. Significant circuit performance improvements are observed through reduced stalls due to contention, and greater memory-access parallelism. On a set of 5 parallel benchmarks, wall-clock time is improved by 2.0x, on average, by the TM synchronization model vs. mutex-based locks.Keywords
This publication has 11 references indexed in Scilit:
- Thread WeavingPublished by Association for Computing Machinery (ACM) ,2019
- Automated generation of banked memory architectures in the high-level synthesis of multi-threaded softwarePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2017
- More than you ever wanted to know about synchronization: synchrobench, measuring the impact of the synchronization on concurrent algorithmsACM SIGPLAN Notices, 2015
- From software threads to parallel hardware in high-level synthesis for FPGAsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2013
- The tao of parallelism in algorithmsACM SIGPLAN Notices, 2011
- LegUpPublished by Association for Computing Machinery (ACM) ,2011
- Transactional memories for multi-processor FPGA platformsJournal of Systems Architecture, 2011
- Dynamic performance tuning of word-based software transactional memoryPublished by Association for Computing Machinery (ACM) ,2008
- Transactional Locking IILecture Notes in Computer Science, 2006
- Fibonacci and Galois representations of feedback-with-carry shift registersIEEE Transactions on Information Theory, 2002