Performance evaluation of FinFET pass-transistor full adders with BSIM-CMG model

Abstract

In this paper, multiple full adder circuits have been implemented using the FinFET device described by the BSIM-CMG model. A variety of adders have been selected to compare the impact of this technology and evaluate the performance advantages that can be achieved. Full adder designs tested in this work include 28 transistor mirror adder, 10 transistor complementary and level restoring carry logic adder and ultra-low power full adder (ULPFA) architectures which cover a broad spectrum of adder designs. Comprehensive simulation results demonstrate FinFET transistors' advantage in key design metrics, including reduced dynamic power, leakage current and delay. Overall, PDP gains of up to 83% is observed when compared to conventional CMOS circuits. However, FinFET pass-transistor circuits without level restorers are shown to be more vulnerable to voltage degradation compared to CMOS counterparts.