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LVCMOS and BLVDS Based Energy Efficient Counter Design on 28nm FPGA
Home
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LVCMOS and BLVDS Based Energy Efficient Counter Design on 28nm FPGA
LVCMOS and BLVDS Based Energy Efficient Counter Design on 28nm FPGA
DM
Devanshi Mahajan
Devanshi Mahajan
DG
Daizy Gupta
Daizy Gupta
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1 July 2015
journal article
Published by
Gyancity Research Consultancy
in
Gyancity Journal of Engineering and Technology
Vol. 1
(2)
,
31-41
https://doi.org/10.21058/gjet.2015.1206
Abstract
No abstract available
Keywords
EFFICIENT COUNTER
COUNTER DESIGN
BLVDS BASED
28NM FPGA
ENERGY
LVCMOS AND BLVDS