Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs
- 12 August 2021
- journal article
- research article
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Reconfigurable Technology and Systems
- Vol. 14 (3), 1-30
- https://doi.org/10.1145/3458843
Abstract
In the current work, we study the process variability of logic, interconnect, and arithmetic/DSP resources in commercial 16-nm FPGAs. We create multiple, soft-macro sensors for each distinct resource under evaluation, and we deploy them across the FPGA fabric to measure intra-die variation, as well as across multiple FPGAs to measure inter-die variation. The derived results are used to create device-signature variability maps characterizing the distribution of variability across the die. Our study includes decoupling of variability to systematic and stochastic parts, exploration of variability under various voltage and temperature conditions and correlation analysis between the variability maps of the different resources. Furthermore, we scrutinize the impact of variability on the performance of actual test circuits and correlate the retrieved results with the sensor-based maps. Our experimental results on four Zynq XCZU7EV FPGAs showed significant intra- and inter-die variability, up to 7.8% and 8.9%, respectively, with a small increase under certain operating conditions. The correlation analysis demonstrated a strong correlation between the logic and arithmetic resources, whereas the interconnects showed a slightly weaker correlation in specific devices. Finally, a relatively moderate correlation was calculated between the variability maps and performance of test circuits due their dissimilar operating behavior versus our sensors.Keywords
This publication has 33 references indexed in Scilit:
- A Survey of Techniques for Approximate ComputingACM Computing Surveys, 2016
- A Survey of Architectural Techniques for Managing Process VariationACM Computing Surveys, 2016
- Intra-die process variation aware anomaly detection in FPGAsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2014
- Low-cost sensing with ring oscillator arrays for healthier reconfigurable systemsACM Transactions on Reconfigurable Technology and Systems, 2012
- Self-Measurement of Combinatorial Circuit Delays in FPGAsACM Transactions on Reconfigurable Technology and Systems, 2009
- A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performancePublished by Association for Computing Machinery (ACM) ,2000
- Subwavelength lithography and its potential impact on design and EDAPublished by Association for Computing Machinery (ACM) ,1999
- Delay fault coverage and performance tradeoffsPublished by Association for Computing Machinery (ACM) ,1993
- Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulasIEEE Journal of Solid-State Circuits, 1990
- Random pattern testability of delay faultsInternational Conference on Acoustics, Speech, and Signal Processing (ICASSP), 1988