A Switched Capacitor Waveform Digitizing ASIC at Cryogenic Temperature for HPGe Detectors

Abstract

This article presents the design and evaluation of the first cryogenic switched capacitor array (SCA)-based waveform digitizer (CryoSCA) for HPGe detectors for low-background physics experiments. The chip has integrated 16 channels and was fabricated using a 0.18- μm CMOS process with modified BSIM3v3 model parameters at 77 K. Each channel employs two 32-cell sample blocks working in the ping-pong mode, a 256-cell storage array, 32 parallel Wilkinson-type ADCs with 12-bits dynamic range, and registers. The chip was fully evaluated and showed promising performance at 300 K and 77 K. The measured power consumption of each channel increased from 3.3 mW at 300 K to 3.6 mW at 77 K. The averaging integral nonlinearity (INL) over 1-V dynamic range was measured to be 0.3% and 0.2% at 300 K and 77 K, respectively. The static noise decreased from 0.8 mV at 300 K to 0.6 mV at 77 K. The leakage current decreased from 18.2 fA at 300 K to 2.2 fA at 77 K.