Efficient SpMV Operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization
Published: 12 October 2019
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture
pp 347-358; https://doi.org/10.1145/3352460.3358330
Keywords: SpMV / custom hardware / merge parallelization / sparse matrices
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