Design and Implementation of a Efficient Router using X Y Algorithm

Abstract

The engineering for on chip network configuration utilizing dynamic reconfiguration is an answer for Communication Interfaces, Chip cost, Quality of Service, ensure adaptability of the organization. The proposed engineering powerfully arrange itself concerning Hardware Modules like switches, Switch based packet , information to a packet size with changing the correspondence situation and its prerequisites on run time. The NOC Architecture assumes urgent part while planning correspondence frameworks intended for SOC. The NOC engineering be better over traditional transport, mutual transport plan , cross bar interconnection design intended for on chip organizations. In a greater part of the NO C engineering contains lattice, torus or different geographies to plan solid switch. In any case, the greater part of the plans are neglects to advance a Quality of Service, blocking issues, cost, Chip as well as mostly plan throughput, region transparency with inactivity. Proposed plan we are planning a reconfigurable switch for network on chip plan that improve the correspondence performance. The proposed configuration dodges the restrictions of transport based interconnection plans which are frequently applied in part progressively reconfigurable FPGA plans. . With the assistance of this switch plan we can accomplish low inactivity and high information throughput.