Optimization of the 65-nm CMOS Linear Front-End Circuit for the CMS Pixel Readout at the HL-LHC
- 4 October 2021
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 68 (11), 2682-2692
- https://doi.org/10.1109/tns.2021.3117666
Abstract
The Linear front-end is the analog processor chosen for the final integration into the pixel readout chip for the High-Luminosity upgrade of the CMS experiment at the Large Hadron Collider. The front-end has been included in the RD53A chip, designed by the CERN RD53 collaboration and submitted in 2017. An optimized version of the front-end has been designed, submitted and tested in the framework of the RD53B developments. The optimization is mainly concerned with the time-walk performance of the front-end and with its threshold tuning capabilities. The paper describes in details such design improvements together with the results from the characterization of a small prototype chip including a 16 × 16 pixel matrix featuring both the RD53A and RD53B version of the front-end. Test results show a significant reduction, about 10 ns for input signals close to the threshold, of the time-walk in the RD53B front-end, featuring a threshold dispersion smaller than 65 electrons r.m.s. after exposure to a total ionizing dose of 1 Grad of X-rays.Keywords
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