Non-Speculative Load-Load Reordering in TSO
- 24 June 2017
- journal article
- conference paper
- Published by Association for Computing Machinery (ACM) in ACM SIGARCH Computer Architecture News
- Vol. 45 (2), 187-200
- https://doi.org/10.1145/3140659.3080220
Abstract
In Total Store Order memory consistency (TSO), loads can be speculatively reordered to improve performance. If a load-load reordering is seen by other cores, speculative loads must be squashed and re-executed. In architectures with an unordered interconnection network and directory coherence, this has been the established view for decades. We show, for the first time, that it is not necessary to squash and re-execute speculatively reordered loads in TSO when their reordering is seen. Instead, the reordering can be hidden form other cores by the coherence protocol. The implication is that we can irrevocably bind speculative loads. This allows us to commit reordered loads out-of-order without having to wait (for the loads to become non-speculative) or without having to checkpoint committed state (and rollback if needed), just to ensure correctness in the rare case of some core seeing the reordering. We show that by exposing a reordering to the coherence layer and by appropriately modifying a typical directory protocol we can successfully hide load-load reordering without perceptible performance cost and without deadlock. Our solution is cost-effective and increases the performance of out-of-order commit by a sizable margin, compared to the base case where memory operations are not allowed to commit if the consistency model could be violated.Keywords
Funding Information
- Vetenskapsrådet (621-2012-5332)
- Ministerio de Economía y Competitividad (TIN2015-66972-C5-3-R)
This publication has 26 references indexed in Scilit:
- An Evaluation of High-Level Mechanistic Core ModelsACM Transactions on Architecture and Code Optimization, 2014
- Efficient sequential consistency via conflict orderingPublished by Association for Computing Machinery (ACM) ,2012
- A Primer on Memory Consistency and Cache CoherenceSynthesis Lectures on Computer Architecture, 2011
- x86-TSOCommunications of the ACM, 2010
- BulkSCPublished by Association for Computing Machinery (ACM) ,2007
- Multifacet's general execution-driven multiprocessor simulator (GEMS) toolsetACM SIGARCH Computer Architecture News, 2005
- Toward kilo-instruction processorsACM Transactions on Architecture and Code Optimization, 2004
- Using speculative retirement and larger instruction windows to narrow the performance gap between memory consistency modelsPublished by Association for Computing Machinery (ACM) ,1997
- Dynamic self-invalidationACM SIGARCH Computer Architecture News, 1995
- Dynamic self-invalidationPublished by Association for Computing Machinery (ACM) ,1995