Antiphase Method of the CMOS Power Amplifier Using PMOS Driver Stage to Enhance Linearity
Electronics , Volume 9; doi:10.3390/electronics9010103
Abstract: We present the possibility of a complementary metal-oxide semiconductor (CMOS) power amplifier (PA) using a driver stage composed of p-channel metal oxide semiconductor (PMOS) to enhance linearity. The PMOS driver stage is designed as a cascode structure to adapt the antiphase technique to the CMOS PA. By biasing the common-source transistor of the driver stage at the subthreshold region, we obtain a gm3 value with a positive sign to cancel out the negative gm3 of the power stage, thereby enhancing the linearity. We also investigate the effect of the bias of the cascode transistor of the driver stage on third-order intermodulation distortion and amplitude-to-phase distortion. Consequently, we show that the PMOS driver stage itself acts as a pre-distorter of the power stage. To verify the possibility of the PMOS driver stage and the proposed biasing method for the antiphase technique, we design a 2.42 GHz PA using a 180 nm RFCMOS process for wireless local area network applications. We obtain a measured maximum linear output power of 21.5 dBm with a 23.4% power-added efficiency and an error vector magnitude of 3.14%. We use an 802.11 n modulated signal with 64-quadrature amplitude modulation (QAM) (MCS7) at 65 Mb/s.
Keywords: CMOS / power amplifier / linearity
Scifeed alert for new publicationsNever miss any articles matching your research from any publisher
- Get alerts for new papers matching your research
- Find out the new papers from selected authors
- Updated daily for 49'000+ journals and 6000+ publishers
- Define your Scifeed now
Click here to see the statistics on "Electronics" .